Is there any cache memory on the 1837?

[lpcware]

Content originally posted in LPCWare by JM_Romero on Tue Nov 18 10:52:34 MST 2014
Hi everybody!

I am developing a Real Time application using this evaluation board, based on the LPC1837 (http://www.nxp.com/demoboard/OM13061.html).

I have observed some non-deterministic behavior in the system. Reading through the User Manual, I found that in the SPI Flash Interface chapter it is said, that there exist a cache memory for improving the system performance. I have not been able to find out either where this cache is placed, or its size. Knowing this information would be really helpfull for my work.

Is there any way for checking if it is enabled?

Regards,

JM_Romero.

[lpcware]

Content originally posted in LPCWare by mc on Sun Nov 23 07:23:51 MST 2014
Hi,
There is cache in SPIFI peripheral to speed up external  SPI/DSPI/QSPI memory access. Using this cache you can perform faster execution from (XIP) External serial flash memory itself.

[lpcware]

Content originally posted in LPCWare by cfb on Sat Nov 22 23:02:11 MST 2014
Did you notice this section? It doesn't say where the cache is but it does explain how you can have some control over it:

19.6.5 SPIFI cache limit register

The SPIFI hardware includes caching of previously-accessed data to improve performance. Software can write an address within the device to this register, to prevent such caching at and above that address. After Reset this register contains the allocated size of the SPIFI memory area, so that all possible accesses are below that value and are thus cacheable.

SPIFI cache limit register (CLIMIT, address 0x4000 3010)