Is the assembly code in the figure below located in bootrom? Can I see the C source code?

[superliyou]

Dear NXP engineers，

      Is the assembly code in the figure below located in boot ROM? 

      It means that Core0 boot address is 0x10003DCC when reset in secure boot? And we can't modify it directly when develop the secure boot ?

      We use the LPC55s69 Development Board. Can you share the C source code in boot ROM? I think this is very helpful for us to understand secure boot.

      thanks a lot!

[ZhangJennie]

Hi

Your screenshot is program flash.

For the boot rom address and description, please see AN11126 attachment. It resides at the end of flash region

Best Regards

Jun Zhang

[superliyou]

Hi Jun,

    Thank you for your patience.

    I see the rom address is  bellow:

   0x0300 0000 0x0301 FFFF 0x1300 0000 0x1301 FFFF Boot ROM, on CM33 code bus.

  Here is my understanding. Help me check.

   So when the chip reset, Core is run in the ROM（boot Rom），the reset SBC-VTOR data is point to ROM address?  OR it is a Hardware mechanism  force CPU reset address to  ROM .

    In the boot Rom , Validate CMPA/NMPA, check PIO0_5 pin, if it is high ,it will look for valid image in the internal flash.   Modify SBC-VTOR/SP/PC according to the image in flash，and then run user code.And we can do a second bootloader in the flash code(for instance,run app code in Sram).

thanks a lot!

[ZhangJennie]

I would suggest you refer https://www.nxp.com/docs/en/application-note/AN12283.pdf

Page2, Figure 1. LPC55S6x/LPC55S2x/LPC552x boot flow chart for 1B. You will be more clear about LPC55s69 boot process after read it.