Content originally posted in LPCWare by DPeters on Wed Mar 07 15:04:05 MST 2012 I'm estimating the M0 core consumes about 20mA while it is in the latched reset state. I'm estimating this by comparing the LCP1850 sleep current to the LCP4350 sleep current. Is there a way of gating off power to the M0 from the M4 without running sleep instructions on the M0? I don't need the extra core (for now).
Content originally posted in LPCWare by DPeters on Mon Mar 19 08:41:25 MST 2012 The M0APP clock branch configuration register is neither read or write, so it does appear that the M0 must be put to sleep from an instruction on the M0.
Content originally posted in LPCWare by Massimo Manca on Sat Mar 17 02:02:40 MST 2012 I didn't find anything may help on the draft user manual.
Also power down modes are controlled by M4 core so seems that all the chip has to be low powered. This is quite correct considering that M0 is consideres as a coprocessor so it is controlled by M4.
I should try to put M0 out of reset and put it in a infinite loop with inside a WFI or a WFE instruction.
