Is it possible "map", "transfer" or "create" IRQn_Handler to other Core?

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Is it possible "map", "transfer" or "create" IRQn_Handler to other Core?

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NXP Employee
NXP Employee
Content originally posted in LPCWare by Witte on Wed Sep 17 06:53:31 MST 2014
Hey there,

I have the following scenario:

I have a LPC4337, the Cortex M4 will control the application and the Cortex M0 will control the peripherical (SPI, GPIO INT e etc).

With the Cortex M0, I want control 5 external interrupts by the GPIO's, but I saw in the "startup file" of the Cortex M0, there is only the Handler  "GPIO4_IRQHandler". When I checked the "statup file" of the Cortex M4, I saw the same "GPIO4_IRQHandler" and the others 7 IRQn_Handler.

The question is... Can I transfer, map or create a GPIO1_IRQHandler, for example, on startup file of Cortex M0?

I need control these PINS by the Cortex M0...

Thanks very much!
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NXP Employee
NXP Employee
Content originally posted in LPCWare by Witte on Fri Sep 19 05:46:08 MST 2014
xianghuiwang,

I will want to control 5 external interrupts, and I need to know what pin trigger the interrupt Handler.
If I use the Group Interrupt, Can I know what pin generate the interrupt? I read the datasheet and I didn't found anything about this.

Thanks
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NXP Employee
NXP Employee
Content originally posted in LPCWare by xianghuiwang on Thu Sep 18 20:08:41 MST 2014
Maybe looking into the group interrupt possibility as well? This way you can at least have two interrupts.
Regards!
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NXP Employee
NXP Employee
Content originally posted in LPCWare by starblue on Thu Sep 18 05:30:30 MST 2014
The reason is a design limitation of the Cortex-M0 core, it supports at most 32 interrupt sources.

So don't hold your breath waiting for more.
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NXP Employee
NXP Employee
Content originally posted in LPCWare by Witte on Thu Sep 18 04:52:24 MST 2014
Thanks for your reply Starblue,

I read this section, but I thought this could be exchanged.

Who know this can be the evolution of ARMs Dual Core =P

Thanks!
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NXP Employee
NXP Employee
Content originally posted in LPCWare by starblue on Thu Sep 18 01:37:34 MST 2014
No.

See UM10503 "8.6.2 Interrupt sources for the Cortex-M0APP", that's all you got.
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