Interleaving four channel I2S data with DMA

iscan · ‎01-04-2023

This question concerns DMA operation to interleave four channels of CODEC data over two I2S ports on LPC55S69.

This application has four CODECs operating in TDM mode, connected to I2S6 and I2S7. RX operation only. I2S6 & I2S7 share common clock. Each TDM frame contains 4x 32bit words. I2S6 and I2S7 are configured for CODEC channels 1+2 and 3+4 respectively. I2S6 and I2S7 are serviced by DMA to transfer data to RAM.

I have the DMA working properly for both I2S6 and I2S7. Two DMA channels interleave data from CODEC channels 1 & 2 and channels 3&4 as expected:

I2S6 buffer: [CH1][CH2] [CH1][CH2] [CH1][CH2] [CH1][CH2]

I2S7 buffer: [CH3][CH4] [CH3][CH4] [CH3][CH4] [CH3][CH4]

I require one buffer with four interleaved channels.

I2S buffer: [CH1][CH2][CH3][CH4] [CH1][CH2][CH3][CH4] [CH1][CH2][CH3][CH4] …

I can’t see the features in the SDK that will allow me to set this up.

I am currently interleaving the data from the two buffers manually (pointers in a loop) as a temporary work around. This uses a lot of CPU and RAM.

Questions:

Is there a way to have the DMA channels servicing I2S6 and I2S7 interleave the data as needed?
Can this be resolved by using a third DMA channel to perform memory-to-memory transfer on the existing I2S6 and I2S7 buffer?
Are there other approaches I have not considered?
Can you confirm I can not capture all four 32-bit CODEC channels in a single I2S port.

iscan · ‎01-12-2023

A week later and we still have not addressed the questions I have asked.

The same information you have provided continues to be incorrect.

From the I2S chapter in the LPC55S69 User Manual (UM11126) Rev 2.1, section 37.2:

TDM (Time Division Multiplexing) with a several stereo slots and/or mono slots is

supported. Each channel pair can act as any data slot. Multiple channel pairs can

participate as different slots on one TDM data line.

Here is a diagram from the same section in the same manual with an example TDM frame with more than four slots:

The “position” field in I2S CFG2 is used to specify the starting bit position for data within a frame. This information is provided, once again, in the same section in the same manual (UM11126) Rev 2.1:

Additionally, as I have clearly indicated twice already, I ALREADY HAVE THIS WORKING, TESTED, AND HAVE ZERO PROBLEMS with two I2S ports servicing a TDM frame with four 32-bit slots.

Any reference to the I2S/TDM interface was only intended to provide context to the DMA problem that I am trying to solve.

To be perfectly clear: I2S/TDM – works with four slots, as intended by the chip designers and documented in NXP user manual. This is further confirmed by my own (WORKING) hardware and firmware. There are no I2S/TDM issues. I don’t need any information on the I2S/TDM operation, and I especially don’t need any more incorrect information. I’m not sure how to be any clearer about this.

Could we PLEASE get to the DMA issue?

I have already indicated in the second message in this thread that the DMA question applies to interleaving data from any peripheral or any fixed address in memory. Please refer to the earlier messages.

What I expect at this point is for NXP to provide some instruction, and/or example code, and/or app-note, or even just a hint on how to address the DMA issue that has already been clearly defined. If you do not have this information, please forward this DMA related question to someone that is familiar with the operation of this part.

And again, please do not address any perceived I2S/TDM issues. Completely not necessary.

iscan · ‎01-06-2023

Thank you XiangJun Rong for your reply. The information you provided is not entirely correct. The LPC55S69 does support multiple slot tdm mode.

I have this working without any issues as described in my original post. Currently I have two DMA channels copying I2S FIFO data into two separate arrays. So, there is no problem with the TDM operation.

The difficulty I described in the original post concerns DMA transferring the data from two different I2S FIFOs in an interleaved operation.

To clarify the problem:

Using DMA, I want to copy two 32-bit words from a peripheral (fixed) address to an array of 32-bit words, then copy two more 32-bit words from a different peripheral (fixed) address to the next two addresses in the array.

In this case the peripherals are I2S6 and I2S7. I2S6 FIFO contains TDM SLOT0 and SLOT1 data and I2S7 FIFO contains TDM SLOT2 and SLOT3 data.

I want the DMA controller to arrange the 32-bit words like this in memory:

[SLOT1], [SLOT2],[SLOT3],[SLOT4], [SLOT1], [SLOT2],[SLOT3],[SLOT4], etc.

I can’t see a way to configure the DMA controller to copy two sets of I2S FIFO words to RAM as described below:

Move two words from I2S6 FIFO to array[n] and array[n+1], increment I2S6 DMA channel destination pointer by another two. At this point the I2S6 DMA channel destination pointer should be array[n+4].
Move two words from I2S7 FIFO to array[n+2] and array[n+3], increment I2S7 DMA channel destination pointer by two
Move two words from I2S6 FIFO to array[n+4] and array[n+5], increment I2S6 DMA channel destination pointer by two
Move two words from I2S7 FIFO to array[n+6] and array[n+7], increment I2S7 DMA channel destination pointer by two
.. continues until array full.

Please let me know if this is unclear.

Thank you,

Ian

xiangjun_rong · ‎01-09-2023

Hi

I see your transfer format, this is the format:

FC6:slot0,slot1,slot0,slot1...

FC7:slot0,slot1,slot0,slot1...

Both of FC6 and FC7 have two slots, it is okay.

You want the DMA to transfer the slot data to memory with the format:

FC6_slot0(32 bits) Base address of memory

FC6_slot1(32 bits) at offset 4

FC7_slot0(32 bits) at offset 8

FC7_slot1(32 bits) at offset 0C

FC6_slot0(32 bits) at offset 0x10

FC6_slot1(32 bits) at offset 0x14

FC7_slot0(32 bits) at offset 0x18

FC7_slot1(32 bits) at offset 0x1C

......

I do not think the DMA has the function to finish the above memory saving task.

i think it is okay for the following format which the DMA can implement:

FC6_slot0(32 bits) Base address of memory

FC7_slot0(32 bits) at offset 4

FC6_slot1(32 bits) at offset 8

FC7_slot1(32 bits) at offset 0C

FC6_slot0(32 bits) at offset 0x10

FC7_slot0(32 bits) at offset 0x14

FC6_slot1(32 bits) at offset 0x18

FC7_slot1(32 bits) at offset 0x1C

......

Hope it can help you

BR

XiangJun Rong

iscan · ‎01-10-2023

Yes that will work. I have been working at this for a while. Can you please add some information or example on how to configure DMA and I2S channels to implement this? Also the slot numbers refer to the TDM frame, so the 32-bit slots are slot 0, 1, 2, and 3 within a 128-bit frame. I can assign arbitrary slots positions to each I2S port so I should be able to get them back into the order I need

Thanks,

Ian

xiangjun_rong · ‎01-12-2023

Hi,

Regarding your remark "the slot numbers refer to the TDM frame, so the 32-bit slots are slot 0, 1, 2, and 3 within a 128-bit frame.", I have said that the I2S module of LPC55xx only supports two slots for example I2S mode with two slots slot0,slot1, slot0,slot1,slot0...., it can not support TDM mode with 0, 1, 2, and 3 within a 128-bit frame. You can generate the Frame with 128 bits, but the data in FIFOWR can not drive to SDA pin for slot2 and slot3.

Because the slot2 and slot3 requires additional registers to control.

I copy the part from UM10912.pdf for LPC546xx, the I2S of LPC546xx can support 4 channels or 8 slots at most.

Hope it can help you

BR

XiangJun Rong

xiangjun_rong · ‎01-05-2023

Hi,

Pls refer to Section 32.5.1 Function Summary in UM11126.pdf, for LPC556x/552x, the I2S module just supports two slots I2S, it do not support multiple slots TDM mode.

But the mimxrt600 family support at most 8 slots TDM mode as the following Pic, I copied from UM11147.pdf.

The additional channel requires more register.

For the LPC553x, there are two FC modules FC6 and FC7 which support 8 slot TDM mode.

Hope it can help you

BR

XiangJun Rong

For LPC55xx

For mimxrt600 family