I have an LPC5410J256BD64QL that I am attempting to connect to with a J-Link Ultra+ for the purpose of flashing. However, I cannot connect to the device at all.
When I try to connect, I get the following error message in MCUXpresso:
S/N: 504302790
License(s): RDI, FlashBP, FlashDL, JFlash, GDB
VTref=3.321V
Target connection not established yet but required for command.
Device "LPC54101J256_M4" selected.
Connecting to target via SWD
Found SW-DP with ID 0x0BB11477
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x04770021)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xF0000000
CPUID register: 0x410CC200. Implementer code: 0x41 (ARM)
Found Cortex-M0 r0p0, Little endian.
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WARNING: Identified core does not match configuration. (Found: Cortex-M0, Configured: Cortex-M4)
**************************
FPUnit: 4 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ F0000000
ROMTbl[0][0]: E00FF000, CID: B105100D, PID: 000BB471 ROM Table
ROMTbl[1] @ E00FF000
ROMTbl[1][0]: E000E000, CID: B105E00D, PID: 000BB008 SCS
ROMTbl[1][1]: E0001000, CID: B105E00D, PID: 000BB00A DWT
ROMTbl[1][2]: E0002000, CID: B105E00D, PID: 000BB00B FPB
Cortex-M0 identified.
Reset delay: 0 ms
Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
**************************
WARNING: CPU did not halt after bootloader.
**************************
**************************
WARNING: CPU did not halt after bootloader.
**************************
PC = 0000224E, CycleCnt = 00000000
R0 = 0004CC45, R1 = 80000000, R2 = 80470000, R3 = 00B71B00
R4 = 00000002, R5 = 00000001, R6 = 00014594, R7 = 20003FA0
R8 = C80C2840, R9 = 380C0800, R10= AC082811, R11= 0C098100
R12= 00000000
SP(R13)= 20003FA0, MSP= 20003FA0, PSP= 04240220, R14(LR) = 0000002F
XPSR = 21000000: APSR = nzCvq, EPSR = 01000000, IPSR = 000 (NoException)
CFBP = 00000001, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 01
FPU regs: FPU not enabled / not implemented on connected CPU.
Downloading file [D:\code\MusicTribe\TH_P0DBD\springboard-dice3\springboard-mcu\Boot\springboard-mcu.hex]...
Writing target memory failed.
Script processing completed.
Unable to perform operation!
Command failed with exit code 1
The LPC5410 chip we are using has an M4 and does not have an M0.
I am able to debug with the J-Link debugger and step through code, so I believe the debugger is connected properly. In addition, at some point in the past I was able to flash the MCU but I had to change computers and now cannot get it working.
I am using the GUI Flash Tool in MCUXpresso to do the flashing. Here is a screen capture of the command that is being sent.
I am running MCUXpresso IDE v11.0.0 [Build 2516] [2019-06-05]. We are using a slightly older version of MCUXpresso for compatibility reasons, but I have also tried the most recent version v.11.2.1 and received the same output.
I have broken it down further by trying to connect to the chip using J-Link Commander and it is clear that I cannot connect to the chip. I received similar output.
SEGGER J-Link Commander V6.86 (Compiled Sep 24 2020 17:33:12)
DLL version V6.86, compiled Sep 24 2020 17:31:31
Connecting to J-Link via USB...O.K.
Firmware: J-Link Ultra V4 compiled Sep 21 2020 16:58:33
Hardware version: V4.00
S/N: 504302790
License(s): RDI, FlashBP, FlashDL, JFlash, GDB
VTref=3.321V
J-Link>connect
Please specify device / core. <Default>: LPC54101J256_M4
Type '?' for selection dialog
Device>connect default
Please specify target interface:
J) JTAG (Default)
S) SWD
F) FINE
I) ICSP
C) C2
T) cJTAG
TIF>s
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>
Device "LPC54101J256_M4" selected.
Connecting to target via SWD
Found SW-DP with ID 0x0BB11477
DPIDR: 0x0BB11477
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x04770021)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xF0000000
CPUID register: 0x410CC200. Implementer code: 0x41 (ARM)
Found Cortex-M0 r0p0, Little endian.
Identified core does not match configuration. (Found: Cortex-M0, Configured: Cortex-M4)
FPUnit: 4 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ F0000000
ROMTbl[0][0]: E00FF000, CID: B105100D, PID: 000BB471 ROM Table
ROMTbl[1] @ E00FF000
ROMTbl[1][0]: E000E000, CID: B105E00D, PID: 000BB008 SCS
ROMTbl[1][1]: E0001000, CID: B105E00D, PID: 000BB00A DWT
ROMTbl[1][2]: E0002000, CID: B105E00D, PID: 000BB00B FPB
I have checked reset pin 64 and it is being held high as it is supposed to be.
I have tried connecting to multiple chips, including hardware that has worked in the past.
Does anyone have a clue as to what might be going wrong? Any help would be greatly appreciated.
