How to set LPC54608 clock to 180 MHz limit?

[tomspiegel]

MPUXpresso tools do not seem to support this part yet. All of the examples in the SDK, use FRO output with a limit of 96 MHz.

[tomspiegel]

BOARD_BootClock180M() worked for me. I did have a problem with the SDRAM, but changing the divider basicConfig.emcClkDiv in board.c from 0 to 1 fixed that. The data sheet specifies the maximum clock to the emc is 100 MHz.

[kerryzhou]

Hi Tom,

   Normally, for the new question customer need to create the new post, about the new SDRAM question, please create a new post about it, we will reply you in your new post.

   Thanks a lot for your understanding.

Have a great day,
Kerry

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[carstengroen]

Thanks Tom,

mine fails a RAM test every time if I go above 75 MHz.

I have my own boards coming in a couple of weeks, I will do some testing on these and see if there is any differences (they also have SDRAM and NAND Flash)

[eli_hughes]

I have successfully gotten it to run at 90MHz (the SDRAM).

Also,   if you use the screen, you will need to adjust the clock divider for the LCD as well at this clock rate.

[carstengroen]

Thanks Eli,

mine fails if I go above 75 MHz. I'm running an extensive SDRAM test on it, and it fails every time.
In a few days I will have my first PCB arriving, I will do some testing on that and see if there is a difference (and if it at all works :smileygrin:)

[kerryzhou · Accepted solution]

Hi Tom Spiegel,

   This is the 180M configuration code, just for your reference:

void BOARD_BootClock180M(void)
{
    /*!< Set up the clock sources */
    /*!< Set up FRO */
    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN);                   /*!< Ensure FRO is on  */
    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                  /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
                                                                being below the voltage for current speed */
    POWER_SetVoltageForFreq(180000000U);             /*!< Set voltage for the one of the fastest clock outputs: System clock output */
    CLOCK_SetFLASHAccessCyclesForFreq(180000000U);    /*!< Set FLASH wait states for core */

    /*!< Set up SYS PLL */
    const pll_setup_t pllSetup = {
        .syspllctrl =  SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U),
        .syspllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)),
        .syspllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
        .syspllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)),
        .pllRate = 180000000U,
        .flags =  PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP
    };
    
    CLOCK_AttachClk(kFRO12M_to_SYS_PLL);        /*!< Set sys pll clock source*/
    CLOCK_SetPLLFreq(&pllSetup);                     /*!< Configure PLL to the desired value */

    /*!< Set up dividers */
    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);                  /*!< Reset divider counter and set divider to value 1 */

    /*!< Set up clock selectors - Attach clocks to the peripheries */
    CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK);                  /*!< Switch MAIN_CLK to SYS_PLL */
    SYSCON->MAINCLKSELA = ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) | SYSCON_MAINCLKSELA_SEL(3U)); /*!< Switch MAINCLKSELA to FRO_HF even it is not used for MAINCLKSELB */
    /* Set SystemCoreClock variable. */
    SystemCoreClock = 180000000;
}

Wish it helps you!

If you still have question, please let me know!

Have a great day,
Kerry

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[carstengroen]

Kerry,

two questions to this:

1) Where is the original code  BOARD_BootClock180M() found ? I have searched in the code both on NXP website and in the Pack from Keil, not to be found ?

2) What is the maximum speed the SDRAM can run at ? When I go to 180 MHz I have to divide the SDRAM clock by 3 to get it to run, if I go with 150 MHz cpuclock I can use a divide by 2 for SDRAM and it works. Doing 180 MHz and divide by 2 to the SDRAM fails (memory check fails)

This is my code for init of clock:

/* Clock and PLL initialization based on the internal oscillator */
void Chip_SetupIrcClocking(uint32_t iFreq)
{
     PLL_CONFIG_T pllConfig;
     PLL_SETUP_T pllSetup;
     PLL_ERROR_T pllError;

     /* Power up the FRO and set this as the base clock */
     Chip_SYSCON_PowerUp(SYSCON_PDRUNCFG_PD_FRO);

     /* Till the PLL is Up use 12MHz FRO as the base clock */
     Chip_Clock_SetMainClockSource(SYSCON_MAINCLKSRC_FRO12MHZ);

     /* ASYSNC SYSCON needs to be on or all serial peripheral won't work.
        Be careful if PLL is used or not, ASYNC_SYSCON source needs to be
        selected carefully. */
     Chip_SYSCON_Enable_ASYNC_Syscon(true);
     Chip_Clock_SetAsyncSysconClockSource(SYSCON_ASYNC_FRO12MHZ);

     /* Setup FLASH access */
     setupFlashClocks(iFreq);

     /* Select the PLL input to the IRC */
     Chip_Clock_SetSystemPLLSource(SYSCON_PLLCLKSRC_FRO12MHZ);

     /* Power down PLL to change the PLL divider ratio */
     Chip_SYSCON_PowerDown(SYSCON_PDRUNCFG_PD_SYS_PLL);

     /* VD3 needs to be powered up too for use of PLL. */
     Chip_SYSCON_PowerUp(SYSCON_PDRUNCFG_PD_VD3);

#if USE_ROM_PLL_API
     /* temporary solution, try the ROM driver, integer divider on the nearest multiplier for now. 
     please note: in Chip_POWER_SetPLL(), output freq = integer Multiply by input frequency. 
     e.g. if iFreq is set to 100MHz, but input freq is 12MHz, integer multiplier results
     output clock = 12 * 8 = 96MHz. */
     Chip_POWER_SetPLL((uint32_t)(iFreq/SYSCON_FRO12MHZ_FREQ), SYSCON_FRO12MHZ_FREQ);
#else
     /* Setup PLL configuration */
     pllConfig.desiredRate = iFreq;
     pllConfig.InputRate = SYSCON_FRO12MHZ_FREQ;
     pllError = Chip_Clock_SetupPLLData(&pllConfig, &pllSetup);
     if (pllError == PLL_ERROR_SUCCESS) {
          pllSetup.flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_ADGVOLT;
          pllError = Chip_Clock_SetupSystemPLLPrec(&pllSetup);
     }
#endif
     
     /* Set system clock divider to 1 */
     Chip_Clock_SetSysClockDiv(1);

     /* Set main clock source to the system PLL. This will drive 24MHz
        for the main clock and 24MHz for the system clock */
     Chip_Clock_SetMainClockSource(SYSCON_MAINCLKSRC_PLLOUT);
}


void Board_SetupMemory(void)
{
     /* Setup SDRAM */
     Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_EMC);
     /* Init EMC Controller -Enable-LE mode */
     Chip_EMC_Init(LPC_EMC, 1, 0, 0);
     Chip_Clock_SetEMCDiv(3);
     /* Init EMC Dynamic Controller */
     Chip_EMC_Dynamic_Init(LPC_EMC, &MT48LC8M16_config, Chip_Clock_GetEMCRate());
}




/* Set up and initialize hardware prior to call to main */
void Chip_SystemInit(void)
{
     
     /* Enable All SRAMs */
     Chip_SYSCON_PowerUp(SYSCON_PDRUNCFG_PD_SRAM0 | SYSCON_PDRUNCFG_PD_SRAM1 | SYSCON_PDRUNCFG_PD_USB_RAM);
     Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_SRAM1);
     Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_SRAM2);
     
     /* Initial internal clocking @180MHz */
     Chip_SetupIrcClocking(180000000);

     /* Setup system clocking and muxing */
     Board_SetupMuxing();
     Board_SetupMemory();

}‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

[tomspiegel]

Kerry, Thank you, that is just what I wanted. I will try this later today or tomorrow.

Carsten, thank you for your code. I am also interested in maximizing SDRAM throughput. I will be testing that in the next few days.