How to find the correct timming values for the SDRAM controller

[lpcware]

Content originally posted in LPCWare by larsjep on Wed Oct 03 08:09:59 MST 2012
Hi,

I having some trouble understanding how the timming values are calculated.

If I look in lpc43xx_emc.c (from the PDL) line 198, there is a comment saying: "// calculated from xls sheet"

Is this xls sheet available somewhere ?

Ex. if I look at the value for DYNAMICRP it is set to 1. (in lpc43xx_emc.c line 198)
This should give a tRP of 2xCLK = 19.6ns (When running at 102Mhz)
But the datasheet for the SDRAM on the Hitex board states minimum 20ns (-7 speed)

Shouldn't the DYNAMICRP be set to 2 then ?
Or should the EMC_CLK_DELAY also be involved in the calculation ?

Also the DYNAMICRAS seems incorrect. This is set to 3 => 39.2ns, but the datasheet for the RAM states minimum 42ns

Best regards
  Lars

[lpcware]

Content originally posted in LPCWare by VijayM on Thu Dec 13 01:14:37 MST 2012
In excel sheet from whered does tSUd in front of CAS1, CAS2, CAS3 is picked?
What is this tSUd?

[lpcware]

Content originally posted in LPCWare by bavarian on Thu Oct 04 04:44:19 MST 2012
Hello Lars,

Of course a lot of things depend on the type of SDRAM connected to the LPC4350.
The Excel file is attached. It contains calculation for a different SDRAM (32-bit SDRAM).
I think the comment "// calculated from xls sheet" was left in the code but the value changed.

However, we are currently reviewing all these drivers for various platforms, if we identify problems we will try to fix them.

There is init code attached which works for the Hitex board, but I wouldn't call it reference code. I know that it works on 96MHz EMC frequency, for 102 MHZ I need to do some tests.

Regards,
NXP Technical Support Team