How do decide the CPSDVSR value (2 to 254) given a Frequency and Pclk to find SCR value.

[lpcware]

Content originally posted in LPCWare by sakethsainarayana on Tue Mar 22 20:29:37 MST 2016
Hey,

I am trying to understand on how to choose a CPSDVSR value i.e., on what basis should i decide this value in order to calculate the SCR value when i have a SPI frequency and Pclk value.

My professor has chosen 32 but hasnt given any explanation about why and how to choose the values.

Any response would help.

Thanks!

[lpcware]

bump

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Wed Mar 23 03:30:17 MST 2016
Most SPI type devices will have a maximum frequency at which they will operate reliably.
Read the data sheet for your device to see what this is for your case.

Mostly, the frequency is quite low e.g. 30 to 50 MHz max.

The PCLK is a simple divided down CPU clock.

This is often quite high (relatively) e.g. up to 120 MHz.

By dividing (or prescaling) the PCLK for the SSP module we get better control (granularity)
of the (integer arithmetic) speeds available in the bit rate formula (see control reg 0 in the UM).

I don't know your numbers, but I would guess that the 32 you mentioned gives a nice 'base' frequency' to work with.

HTH, Mike.