Some questions on the External Memory Controller (EMC) on the LPC43xx:
Reference, per App Note 11508:
See section 2.2.5.3 Best performance using a single SDRAM device and CCLK Div2:
Hi Micheal,
For item 1, I guess the reason is "Since CLK1 and CLK3 are not being used as feedback clocks their length may exceed the 6” restriction without affecting the feedback clocks for capturing SDRAM read data".
For itme2-1, yes. For item2-2, using CLK0 and CLK2 to drive FBCLK and CLK1/CLK3 to drive SDRAM is more PCB friendly, this is related to item1 that you can have longer CLK1/CLK3 traces on PCB
Best regards
Rocky Song