Help on configuring PLL on LPC3131

[lpcware]

Content originally posted in LPCWare by BasicPoke on Tue May 10 08:50:34 MST 2016
On the LPC3131, can I please get some help on how to set up the PLL for a certain frequency.  I am not really understanding the documentation in the user manual UM10314.  Here is the sample code I have.  Do I only need to set the 3 dividers?

  //PLL Init 180MHz
  HP1_MODE = 0x4;     //Power Down PLL

  HP1_FIN_SELECT = 0; //Select FFAST as Pll input clock
  HP1_MDEC = 8191;    //M divider
  HP1_NDEC = 770;     //N divider
  HP1_PDEC = 98;      //P divider

  HP1_SELR = 0;
  HP1_SELI = 16;
  HP1_SELP = 8;

  HP1_MODE = 1;       //Enable PLL

  while(!(HP1_STATUS & 1)); //Wait untill PLL locks

Also, I am seeing 90 MHz on the CLOCK_OUT signal.  Is it normal for this to be the main clock divided by 2?

Thanks for any help.
Ron

[lpcware]

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[lpcware]

Content originally posted in LPCWare by BasicPoke on Tue May 10 12:01:50 MST 2016
I don't know which mode the PLL is using in my example.  The code sets HP1_MODE = 1.  Does this mean 1a, 1b, 1c, or 1d?  The only mode that uses the post-divider P indicates that P can be set to 1 to 32, but then the table on page 288 shows values of P outside of this range (66 and 98).  I have tried the equations listed for Modes 1a, 1b, 1c, and 1d and none of them match table 298.  I have found that when I use settings from this table, my output frequency appears to match that in the table (CLOCK_OUT is Fout / 2).  The table works but I don't know why.  For example:

  HP1_MDEC = 1023;    //M divider
  HP1_NDEC = 770;     //N divider
  HP1_PDEC = 10;      //P divider
  HP1_SELR = 0;
  HP1_SELI = 16;
  HP1_SELP = 7;

Table 298 indicates Fout = 24 MHz and I measure 12 MHz on CLOCK_OUT, which I believe would be correct.  Can anyone shed some light on this?  Is it possible for me to use Fout = 12 MHz.  I don't see any logic here that tells me how to do this.
Thanks
Ron