Having trouble reading data in SSP0_MISO in a LPC1857 part

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Having trouble reading data in SSP0_MISO in a LPC1857 part

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alejandrocelery
Contributor I

Hi!

I'm having trouble reading an SPI peripheral (an SC16IS740) using a LPC1857.

The problem is that when I read the DR register, it ALWAYS returns 0xFF.

I am using pin P3_7 in function 2 with the following configuration:

#define PIN_MODE_MXSX_FUNC(n)    (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | ((SCU_MODE_FUNC0)+n))

I read data using:

uint8_t r;

Chip_SSP_ReadFrames_Blocking( LPC_SSP0, &r, 1 );

When I debug my code the Chip_SSP_ReadFrames_Blocking call I see the proper execution flow:

Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) returns true before I read the received frame and I see the status RNE status flag go to 0 after the read.

I have checked with a scope that the P3_7 line has the correct reply from the device when there is no data: 0x60.

I have tried the exact same code on SSP1 and it works perfectly.

It seems like I am making a mistake when configuring the SSP0 device or that there is something missing in the documentation. Perhaps an interaction with the boot procedure (since SSP0 is a possible boot code source)? I checked everything that I could think of, please help me with these problem.

Best regards,

Alex

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi Alex,

    You said, you test the MISO wave, it is correct.

   Could you please also test all the SPI wave, CS, SPI_MISO,MOSI, CLK.

   Check both SSP0 and SSP1, then attach the wave.

   Please also attached the code. In the initialization, and SPI operation code, did you use the same code, just with different SPI interface?

  About the pin configuration, I check your post code, it is correct, the official code is :

    if (pSSP == LPC_SSP0) {
        /* Set up clock and power for SSP0 module */
        /* Configure SSP0 pins*/
        Chip_SCU_PinMuxSet(0x3, 3, (SCU_PINIO_FAST | SCU_MODE_FUNC2));    /* P3.3 connected to SCL/SCLK    SCU_MODE_FUNC2=SSP0 SCK0 */
        Chip_SCU_PinMuxSet(0x3, 6, (SCU_PINIO_FAST | SCU_MODE_FUNC2));    /* P3.6 connected to nCS        SCU_MODE_FUNC2=SSP0 SSEL0 */
        Chip_SCU_PinMuxSet(0x3, 7, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2));    /* P3.7 connected to SO        SCU_MODE_FUNC2=SSP0 MISO0 */
        Chip_SCU_PinMuxSet(0x3, 8, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2));    /* P3.8 connected to nSI    SCU_MODE_FUNC2=SSP0 MOSI0 */
    }
    else if (pSSP == LPC_SSP1) {
        /* Set up clock and power for SSP1 module */
        /* Configure SSP1 pins*/
        Chip_SCU_PinMuxSet(0xF, 4, (SCU_PINIO_FAST | SCU_MODE_FUNC0));    /* PF.4 connected to SCL/SCLK    SCU_MODE_FUNC0 = SSP1 SCK1 */
        Chip_SCU_PinMuxSet(0xF, 5, (SCU_PINIO_FAST | SCU_MODE_FUNC2));    /* PF.5 connected to nCS        SCU_MODE_FUNC2 = SSP1 SSEL1 */
        Chip_SCU_PinMuxSet(0xF, 6, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2));    /* PF.6 connected to SO              SCU_MODE_FUNC2 = SSP1 MISO1 */
        Chip_SCU_PinMuxSet(0xF, 7, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2));    /* PF.7 connected to nSI          SCU_MODE_FUNC2 = SSP1 MOSI1 */
    }

I think, you also need to check the hardware, whether P3_7 connect to the chip correctly, especially the external wire to the chip pin, you need to make sure this pin didn't connect to other module.


Have a great day,
Kerry

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alejandrocelery
Contributor I

Hello Kerry!

I have found and solved the problem. It was somewhat weird: I was reading the SSP0-MISO pin at P1_1-F5, but pin PF_2 was also configured as SSP0-MISO (function 2), so the 0xFF seemed to be coming from this pin.

The funny thing is that my code does not make a Chip_SCU_PinMuxSet call to set PF_2 at function2 and yet it was not in it's default function 0 setting. Pin F_2 function 0 is listed in the UM as "reserved", maybe this is why it doesn't select function 0 at default? Could you please look into this and give me a reply?

The problem was solved by setting PF_2 as GPIO (function 5) and then the only SSP0-MISO was the desired P1_1-F5.

Again, please look into this matter, the possible implication is that every time a configure a pin as a peripheral I'd have to check if there is another pin without function 0 that could possibly be hijacking the desired peripheral function.

Best regards,

Alex

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi Alex,

   Thank you for your updated information.

  You said:

I have found and solved the problem. It was somewhat weird: I was reading the SSP0-MISO pin at P1_1-F5, but pin PF_2 was also configured as SSP0-MISO (function 2), so the 0xFF seemed to be coming from this pin.

Did you debug the code, and check SFSPF_2 register, bit 2-0(MODE), whether it is 0 or function 2?

If you use PF_2, and just leave P1_1 as the default definition, can you receive the SPI DATA correctly?

Have a great day,
Kerry

 

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alejandrocelery
Contributor I

Hi Kerry!

I did debug the SFSPF_2 register, bit 2-0(MODE), and it was in fact function 2. Actually, that's how I discovered the problem.

I did NOT use PF_2, and leave P1_1 as the default definition, I'm working on a production PCB and pin PF_2 is not accesible.

The one thing I did not try is to put a data watchpoint on SFSPF_2 to check if it was my software changing the default configuration. I will do it later.

In the meantime, could you check to see if registers with function 0 listed as "reserved" still have the SFS register by default in function 0 or if they move to some other available pin function?

Best regards,

Alex

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi Alex,

    Thank you for your updated information, I will try it on my lpc1857 board.

    Any updated information from my side, I will let you know!

   Now, you can use your own solutions at first.


Have a great day,
Kerry

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alejandrocelery
Contributor I

Hello Kerry! Thanks for taking the time to help me. Below are my comments:

"Could you please also test all the SPI wave, CS, SPI_MISO,MOSI, CLK."
   I have looked at the four lines with a logic analizer and they are all OK.

"Check both SSP0 and SSP1, then attach the wave.
Please also attached the code. In the initialization, and SPI operation code, did you use the same code, just with different SPI interface?"
   I have looked at the four lines on both SSP with a logic analizer and they are all OK.

"I think, you also need to check the hardware, whether P3_7 connect to the chip correctly, especially the external wire to the chip pin, you need to make sure this pin didn't connect to other module."
    I have checked this and it's OK too.

At this point I'm afraid that there is some aditional configuration to be done for using the SSP0 peripheral that I'm not aware of. Can you tell me if this is the case?

Most importantly, I have tried this with an LPCXpresso V3 board (with LPC18s37 MCU) connecting the SC16IS740 through the pins on the J3 (PMOD) connector and the problem is exactly the same.
Could you please provide an example of reading an SPI slave peripheral with the mentioned board that I could use as a starting point?

My initialization code:
#define PIN_MODE_SCK_FUNC(n)    (SCU_PINIO_FAST | ((SCU_MODE_FUNC0)+n))
#define PIN_MODE_MXSX_FUNC(n)    (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | ((SCU_MODE_FUNC0)+n))

Chip_SCU_PinMuxSet    ( 0x3, 3, PIN_MODE_SCK_FUNC(2) );    //SCK
Chip_SCU_PinMuxSet    ( 0x3, 7, PIN_MODE_MXSX_FUNC(2) );    //MISO
Chip_SCU_PinMuxSet    ( 0x3, 8, PIN_MODE_MXSX_FUNC(2) );    //MOSI
//The SSEL pin is handled through GPIO function. I checked it with the LA and it's OK.

Chip_SSP_Init        ( LPC_SSP0 );
Chip_SSP_SetFormat    ( LPC_SSP0, SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_MODE3 );
Chip_SSP_SetBitRate    ( LPC_SSP0, 100000 );
Chip_SSP_Enable        ( LPC_SSP0 );

Regards,

Alex

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