Halt at EMC access

[Seiichiro]

Hi. 
I am facing EMC access problem in LPC4367 board.

In my  LPC board, FPGA is connected to LPC4367 as static memory.
But sometime CPU looks halted when EMC memory access.

It happens about 30% of power up case, and manual /RESET can not recover this situation,  

I checked EMC registers, and found EMC busy bit=1 when  HALT.
once BUSY goes "1", I can not make it  "0" by EMC reset and EMC restart.

do you know similar problem? 

[xiangjun_rong]

Hi,

The EMC->STATUS[Busy]  setting means that the EMC is performing memory transaction,it does not give more inf.

Pls try to use a scope or logic analyzer to display the address/data/control signal timing so that we can check the timing issue.

BTW, I suppose that you simulate the FPGA timing with SRAM timing and the PB bit is 1. Pls make sure that WAITWR value in STATICWAITWRx reg must be greater than WAITWEN in STATICWAITWENx reg.

The reading timing also has the same requirement, the WAITRD value must be greater than WAITOEN value.

Hope it can help you

BR

XiangJun Rong

[Seiichiro]

Thank you for your advise.

In my case,  When MPU tries to accses external memory, /CS is not asserted  and ADR/DATA bus line looks "silent".

 When  EMC Status BUSY bit is HIgh, MPU halted at accessing memory. And if status is not BUSY,
memory accsess completed nomally.

and I can not find how to negate BUSY.

[xiangjun_rong]

Hi,

Do you use the external SRAM to save data or code? if you use it as code and execute code from external SRAM, you have to initialize the MPU so that the external RAM address space can be execution enabled.

Pls refet to the an12423.pdf

https://www.nxp.com/docs/en/application-note/AN12423.pdf

Hope it can help you

BR

XiangJun Rong