Content originally posted in LPCWare by larsjep on Tue Jan 14 01:26:56 MST 2014
Hi,
I have a problem with the Ethernet controller when using a DP83620SQ Phy.
This Phy should be more or less compatible with the the DP8384 on the Hitex eval board.
The problem is that sometimes at startup I keep getting ethernet interrupt.
If I check the DMA_STAT register none of the interrupt bits is set.
But if I check MAC_INTR bit 10 it set, when the problem occurs ??
According to the manual this bit is just "reserved"
This bit get set right after I send a reset command to the Phy. (But only sometimes)
What is the meaing of this bit 10 in the MAC_INTR register ?
And why does it get set ?
Best regards
Lars
