In that case, is there a minimum cclk freq at which the Ethernet module will operate correctly? Or can we simply say - lower is the cclk lesser is the MCU response time?
For the LPC407x only...
For general clocking when enabling the ethernet clock via the System and Clock Control block, it's CCLK. MDIO data transfer is via the ethernet RX_CLK/TX_CLK pin clocking (usually 25MHz (MII) or 50MHz (RMII). Internal data transfers (DMA descriptors and buffers) are on the internal AHB bus at CCLK rate.