Ethernet IEEE 1588 target time register

[matteo_vit]

Hi,

in the LPC540xx user guide (UM11060), page 831, there is the flag TSTRIG

"Enable timestamp interrupt trigger.
When this bit is set, the timestamp interrupt is generated when the system time
becomes greater than the value written in the target time register. This bit is reset
after the timestamp trigger interrupt is generated."

But I can't find the target time register, so I am not sure when the interrupt is going to be triggered.

Is this feature implemented?

Thanks,

Matteo

[ppardo]

Hi

do you have a reply to your question ?

I've got exactly the same (where is the target time register for the TSTRIG) in my lpc54s018, but nothing in the documentation, and nothing in NXP forums

Any advice will be welcome

regards

[ZhangJennie]

Hi Matteo

I sent you message for more information needed.

Please have a look.

Thanks!

Jun Zhang

[ppardo]

Hi ,

I need this reply too.

In documentation, for TSIS, where's the target time registers ?

Timestamp interrupt status.
This bit is set when any of the following conditions is true:
The system time value equals or exceeds the value specified in the target time
high and low registers.
There is an overflow in the seconds register.
This bit is cleared on reading the byte 0 of the timestamp status register
(Table 798).
When default timestamping is enabled, this bit when set indicates that the system
time value equals or exceeds the value specified in the target time registers. In this
mode, this bit is cleared after the completion of the read of this interrupt status
register[9]. In all other modes, this bit is reserved.