Does EMC memories have priorities?

[priyankb]

Hi everyone,

I recently came across a strange behavior. I have a custom board with LPC4088 interfacing to

1. Nor-flash(SST39vf3201C) connected to CS3
2. SRAM(CY62157EV30LL-45ZSXI) connected to CS1 &
3. FPGA connected to CS0.

I use USB bootloader which is in internal flash & user application is stored in EMC Nor-flash. In normal condition user application works fine but when I use LCD it slows down too much. So I checked signals in oscilloscope & found out that SRAM is read too much, so flash does not get time to execute. In short SRAM making flash slow.

In ARM PrimeCell Multiport Memory Controller reference manual I read

The memory controller AHB memory ports are prioritized. If a master connected to a HIGH priority port performs continuous transactions, lower priority ports are not able to access the bus until the higher priority port has completed its transactions.

Lower priority AHB memory ports can be locked out indefinitely if a higher priority AHB memory port continually performs memory requests

When I replicate the same thing in evaluation board of LPC4088 with same Nor-flash connected to CS0 & SDRAM(instead of SRAM) connected to DYCS0, everything works properly.

Is there priorities between EMC memories?

Does it mean I have to swap CS lines of FPGA & Nor-flash in order to make things normal?

Any useful suggestions are appreciated.

Thank you.

Priyank.

[soledad]

Hi, 

Please check the application note AN11508, you will find some recommendation for Shared EMC configuration (page 17): 

https://www.nxp.com/docs/en/application-note/AN11508.pdf 

Have a great day,
Sol

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[priyankb]

Hi Sol,

Thank you for the reply. I read this application note, but it is still not clear if I must use bus buffers if only static memories are used. Since in my project all the memories are static.

I also read this in application note AN10950:

When using a mixture of dynamic and static memories it is recommended that all signals being used in the static memory bus are buffered prior to arriving at memory devices.

So the question is even if i do not use dynamic memories, is bus buffers necessary for multiple static memory implementation?

Regards

Priyank.