Hi, Sergii,
This is only my guess, as you know that the ADC analog channel is connected to a S/H(sample/hold), which is a capacitor actually. In the sampling phase, the sampling route is connected, the external signal source charges the capacitor of S/H, while the holding route is disconnected. In the Holding phase of S/H component, the sampling route is disconnected, the holding route is connected, the ADC converter samples the voltage of the capacitor of S/H.
I suppose that the your external signal source has not enough driving capacitor, in other words, the external signal source can not provide enough current to charge the capacitor, which leads to the voltage drop. I suggest you use a signal buffer with OP amplifier, for example, connect the tested signal to the non-inverter of OP AMP, connect the inverter pin of AMP to the output pin of AMP, connect the output pin of AMP to ADC analog channel. The AMP output has low impedance and high driving capability.
Pls have a try.
BR
Xiangjun Rong