Correct settings for EMC to connect SDRAM ISSI IS42S32160F to LPC4367

[skiebooms]

I am looking for information/settings for the LPC4367 EMC memory controller to operate the IS42S32160F SDRAM.

I am getting strange behaviors (looks like random 'systematic' data corruption) when the platform is run at full speed.

using the IAR CMSIS EMC project as my test program.

If anybody has any insights would be appreciated. I am new to SDRAM setup so I am trying to understand what is going on.

[jeremyzhou]

Hi Stefaan Kiebooms,

Thank you for your interest in NXP Semiconductor products and 

for the opportunity to serve you.

Please check the attachment which illustrates how to properly interface SDRAM memory to the LPC18xx and LPC43XX external memory contorller.

Have a great day,

TIC

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[skiebooms]

Hi Jeremy: Thanks, I am familiar with AN11508 I have found it of limited use (too many details), it was looking for step by step instructions on how to do connect SDRAM and what information is needed and how to find it in an SDRAM datasheet, which AN11508 does not appear to offer. 

In any case, I got my SDRAM working: key settings were the DYNAMICCONFIG[0] register for the correct 'geometry' of the chip, and having the appropriate burst size (which gets programmed by asserting the address lines of the SDRAM chip) was the second key parameter. Thanks!

[skiebooms]

The problem I am seeing is that about every 0x800 bytes there is a block of garbage in memory spanning a multiple of 16 bytes (1, 3 ...) . Not sure to what setting this behavior correlates?