Hello NXP,
I want to clarify a few things regarding the SGPIO for LPC 43XX.
3. We have a loopback set-up in our board. SGPIO 8 serves as a clock input of SGPIO 0 and SGPIO 1. SGPIO 10 serves as data input to SGPIO 1. We set-up the slice corresponding to SGPIO 1 clk capture mode to use the rising clock edge, so that we can save the data at the falling edge. However, for some reason, this behavior is not seen in my tests on my board. The performance varies between runs.
Hello @marvincabuenas
1)Try to configure as below:
2) The qualifier can be Disable by setting QUALIFIER_MODE=1, resulting in no shift_clk.
3) About this question, recommend you refer to
20.8.1.1 I2S slice selection of user manual, and some application notes about SGPIO:
BR
Alice