Clarification questions on SGPIO for LPC 43XX

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Clarification questions on SGPIO for LPC 43XX

1,038 Views
marvincabuenas
Contributor II

Hello NXP,

I want to clarify a few things regarding the SGPIO for LPC 43XX.

  1. When using the slice mux cfg register, is there a way to invert the external input clock?
  2. When using a qualifier for sgpio mux cfg register, is there a way to only use it once on a periodic signal? This means, we only want to use the qualifier on the first detection of an input slice.

3. We have a loopback set-up in our board. SGPIO 8 serves as a clock input of SGPIO 0 and SGPIO 1. SGPIO 10 serves as data input to SGPIO 1. We set-up the slice corresponding to SGPIO 1 clk capture mode to use the rising clock edge, so that we can save the data at the falling edge. However, for some reason, this behavior is not seen in my tests on my board. The performance varies between runs.

Labels (1)
0 Kudos
Reply
1 Reply

1,006 Views
Alice_Yang
NXP TechSupport
NXP TechSupport

Hello @marvincabuenas 

1)Try to configure as below:

Alice_Yang_0-1689130938556.png

2) The qualifier can be Disable by setting QUALIFIER_MODE=1, resulting in no shift_clk.

3) About this question, recommend you refer to 

20.8.1.1 I2S slice selection of user manual, and some application notes about SGPIO:

https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mc...   

 

BR

Alice

 

 

0 Kudos
Reply