I have a technical question on the LPC54102. For the DMA/ADC combination, it looks like a maximum of 1024 ADC samples can be stored with a single DMA transfer sequence. However, the DMA system allows chaining sequences via the RELOAD feature. My question is, in this case, do we get a perfectly timed ADC transfer rate across that boundary. In other words, I want 2000 ADC samples at a very constant 5 Msps all DMA'd directly into SRAM. Can this be accomplished with no chance of sample timing noise on the ADC, and no dropped samples?
Hi Chris,
I think you can use DMA channel chaining to implement this function and if you also use other DMA channels, you may need to set this DMA channels(for ADC) is highest priority to avoid sample dropped.
Have a great day,
Sol
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