AN11175 DALI master bus receive

[lpcware]

Content originally posted in LPCWare by purplexed on Thu Jun 26 06:03:10 MST 2014
I was analyzing the AN on the subject and I' ve observed a misaligned information between the schematic of the board and the sample code.
In the schematic, DALI bus reception line is connected on TIMER 0 capture 0 and on TIMER 1 match 0, while the code configures and uses timer1 capture and match channels only.
Capture is used to manage the backward frame, but in this case it seems not to care about it because of the improper configuration; so the application works but responses from dali bus appear as always true because the line can't be sampled.
Am I wrong?

[lpcware]

Content originally posted in LPCWare by Irving on Tue Aug 05 00:14:40 MST 2014
Hi purplexed,

It's a good question, and you analyzd very carefully. Actually, we didn't use timer1 match0 function, but we use PIO1_1 as GPIO. The timer0 capture0 is used as capture the DALI bus Rx pin timer count between rising and failing edges. And PIO1_1 is used as GPIO to read DALI bus Rx pin level (Low/High). Thank you.