0x40000220 <- 56: no documentation for this address

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0x40000220 <- 56: no documentation for this address

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loudpotato
Contributor I

Hi. I trying to play with LPC845 and noticed a sample project in MCUXpresso writes 56 to 0x40000220. The LPC845 documentation says nothing about this memory location. Is something correct? Are there other registers that I could adjust? The memory map says the watchdog is located there, but it has no 0x0220 registers.

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Alice_Yang
NXP TechSupport
NXP TechSupport

Hello loudpotato,

Sorry for my last comment.

For LPC845, I think this code for enable SRAM is wrong. maybe this is just copy from other part, for example LPC546xx, enable SRAM register address is 0x40000220 as below:

Alice_Yang_0-1621306469590.png

For LPC845, address should be 0x4004 8080, while it enabled by default, so the demo also can work well, see below:

Alice_Yang_1-1621306587875.png

 

Hope it can help you.

 

BR

Alice

 

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loudpotato
Contributor I

Hi Alice, thank you for looking into this. This is what lpc845breakout_led_blinky says:

 

//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
__attribute__ ((section(".after_vectors.reset")))
void ResetISR(void) {

// Disable interrupts
__asm volatile ("cpsid i");


// Enable SRAM clock used by Stack
__asm volatile ("LDR R0, =0x40000220\n\t"
"MOV R1, #56\n\t"
"STR R1, [R0]");

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Alice_Yang
NXP TechSupport
NXP TechSupport

Hello loudpotato,

This address doesn't release on UM, from the comment, it shows // Enable SRAM clock used by Stac

this is no issue, the demo also can work well.

 

BR

Alice

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loudpotato
Contributor I

Could you please consider updating the UM? I believe the UM should be the source of the truth, not your code examples.

Do you know if writing 56 to 0x40000220 is mandatory? Are there other values could be written there (e.g. for running at 30kHz or at 3kHz)? Are there other registers around I could be missing from other examples, e.g. 0x40000224 or 0x4000021C?

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Alice_Yang
NXP TechSupport
NXP TechSupport

Hello loudpotato,

Sorry for my last comment.

For LPC845, I think this code for enable SRAM is wrong. maybe this is just copy from other part, for example LPC546xx, enable SRAM register address is 0x40000220 as below:

Alice_Yang_0-1621306469590.png

For LPC845, address should be 0x4004 8080, while it enabled by default, so the demo also can work well, see below:

Alice_Yang_1-1621306587875.png

 

Hope it can help you.

 

BR

Alice

 

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Alice_Yang
NXP TechSupport
NXP TechSupport

Hello loudpotato,

Which demo? Please show me when writes 56 to 0x40000220, thanks.

 

BR

Alice

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