Dear Community User, We recently migrated content from the LPCWare.com forums into this community site. Migrated content can be found in the following two locations: LPCXpresso IDE for content from the LPCXpresso folder on the LPCWare.com forum, and LPC for all other content. All imported content will appear as posted by "LPCWARE" and will have the following message displayed at the top of each thread with the original username and date posted in LPCWare: If you wish to find the content you created in LPCWare you must: 1.-  Open the search box at the top right side of your community near your avatar. 2.- Type in the username you had set up in LPCWare and the results should automatically appear. All responses to postings in the original LPCWare.com forums are also preserved, so if you are looking for a response you or another particular user posted then you should also be able to locate those responses using the same search mechanism. All FAQs have been migrated to the NXP Community site. Several forum postings include references to FAQs and re-directs are in place to take you to their new location from those postings.

This content was originally contributed to lpcware.com by Dirceu Rodrigues Introduction My work evaluating the SCT peripheral with the Hitex LPC4350 board (ARM Cortex-M4/M0) included the generation of non standard PWM signals for use in Power Electronics. At the end, some results would be compared with solutions based on LPC1114 (Cortex-M0), for example.  The first idea was to apply a concept that I had used when developing universal controllers for laser printer fuser, at 2001. This is a gate drive for MOSFET / IGBT isolated by pulse transformers. Two pulses Gate Drive – LPC1114 solution The circuit is implemented with pulse transformers (20 kHz PWM frequency) using the gate-source capacitance as memory. A Schottky diode avoids the stored charge to leak through windings. Thus, it's possible to achieve duty-cycles near to 0 and 100 %, simply applying 1 µs pulses shifted in time - one for charge, other for discharge. A very simplified schematic is shown in Figure 1.       Figure 1. Simplified circuit. My solution for the LPC1114 - Cortex-M0, uses two timers in a different scheme: Phase-out or lead/lag the counter values. With CT32B0 and CT32B1 32 bit timers, the behavior, including the pulsed outputs, is better understood looking on Figures 2 and 3 for duty-cycles of 75% and 25%. As opposed to common solutions, for each timer, the MR0 and MR1 matching registers values are constant. The difference between them is equivalent to pulse width (1 µs). The MR0 value also defines the period. The duty-cycle it’s determined through the expression:   DC = TC1 / MR0                                   (1) Where, TC1 is the CT32B1 timer value when this one, for the CT32B0, is zero.      In order to change the duty-cycle, the code in foreground task establishes a new TC1 and enables the CT32B0 overflow interrupt, where  this value is effectively loaded on CT32B1 timer in a safe point (to avoid jitter and other dangerous edges on outputs). Also, the CT32B0 ISR disables itself at the end, ensuring low interrupt overhead. For safety, the first applied pulse is a “discharge pulse”. This solution was proven driving a 930 W (120V/8.7 A) single-phase induction motor and it can be seen in reference [1], using a synchronous AC version of circuit shown in Figure 1 (no diode, four mosfets).      Figure 2. LPC1114 Two Pulses Gate Drive solution - DC 75%.  Figure 3. LPC1114 Two Pulses Gate Drive solution - DC 25%.      Two pulses Gate Drive – LPC4350 SCT solution The equivalent SCT implementation for the Two Pulses Gate Driver has the advantage of saving one timer. The pulse generation can be accomplished through a Mealy finite state machine plus the companion SCT counter. The LPC4350 generates 1 µs pulses with repetition rate of 20 kHz on CTOUT_4 and CTOUT_5 outputs. Two pushbuttons allow that a falling edge on CTIN_2 input, start the timer and a low value on CTIN_6, stop it. The counter operates as a unified 32 bit timer (UNIFY = 1) counting up and down (BIDIR = 1). ADC0 input is used to read the voltage on R26 potentiometer. So, the firmware can convert it in PWM change. As for LPC1114, the LPC4350 core and SCT runs in 48 MHz. Register MATCH 0 defines half-period. The difference between MATCH 2 and MATCH 1 registers is equivalent to pulse width (1 µs). In other words: PULSE_WIDTH = MATCH 2 - MATCH 1                       (2) Despite this difference be constant, now the MATCH 2 and MATCH 1 contents must change at the same time. Figures 4 and 5 show the waveforms for duty-cycles 15 % and 85 %. For example, the duty-cycle can be determined through the expression: DC = 1 – (MATCH 1 + 0.5*PULSE_WIDTH )/ MATCH 0        (3) Figure 4. SCT Two Pulses Gate Drive solution - DC 15%. Note: In companion source code, the PULSE_WIDTH is referred as PULSE_LENGTH. Figure 5. SCT Two Pulses Gate Drive solution – DC 85%. In order to achieve this behavior, one simple Finite State Machine with two states has been defined (Table 1): STATE Meaning 0 CTOUT_4 pulse generation 1 CTOUT_5 pulse generation Table 1. Definition of states. Figure 6 illustrates the relationship between the counter, states and interrupts. The PWM updating scheme takes advantage of following SCT property (as stated on User Manual): “A MATCH register is loaded from the corresponding MATCHREL register when BIDIR is 1 and the counter reaches 0”. In this application, the ADC0 interrupts MCU in a 24 Hz rate, triggered by TIMER0 MR0 (EM0 rising edge). The code on this ISR determines the new MATCH 1, saves it on global variable match1 and enables the SCT interrupt associated with event “counter reach limit” - in fact, event for MATCH 0. Here note, as stated in expression (3), that DC depends only on MATCH1, since MATCH 0 is constant. The ISR code for MATCH 0 event, updates MATCHREL 1 and MATCHREL 2 registers based on variable match1. Also disables the associated interrupt for low overhead. When counter reaches 0, the MATCH 1, 2 registers will be reloaded from the MATCHREL 1, 2 values automatically. This procedure should avoid jitter and other dangerous edges on outputs. Note that MATCH registers are never handled by software when counter is running. The new desired values are indirectly loaded on MATCHREL registers. The first values for MATCH registers are intentionally unreachable (> MATCH 0). This ensures that only ADC readings brought useful values to them. The on board potentiometer generates a voltage from 0 V to 3.3 V, which translates to 0 – 1023 range by the 10 bit AD converter. The MIN_MATCH1 and MAX_MATCH1 predefined values equates to 36 and 1116 (equivalent to duty-cycle 5 % and 95 % DC). Therefore, the software relates ADC0 voltage to with match1 variable approximately through the expression: match1 = [(MAX_MATCH1 - MIN_MATCH1)*ADC0] / 1024 +            (4)                                                  MIN_MATCH1 Note: In the companion source code, the division by 1024 is performed with a 10 bit right shift.           Figure 6. PWM updating scheme - DC 50%. Table 2 lists the eight states comprising the state machine for the current application. The companion state transition diagram is showed on Figure 7. Here, note other SCT important property, as stated on User’s Manual: “If more than one event associated with the same counter occurs in a given clock cycle, only the state change specified for the highest-numbered event among them takes place”. This applies to events 6 and 7. In normal operation, the event 6 happens periodically in State 1; but when a pushbutton press causes a low level on CTIN_6, the event 7 is fired on State 1 and counter is stopped. The state is driven to 0, with the outputs cleared (until one falling edge on CTIN_2 initiates the counting). EVENT ID Happens in state Conditions Actions 0 0 Falling edge on CTIN_2 Start counter 1 0 Counter reach MATCH 1 when counting up Set CTOUT_4 (pulse rise) 2 0 Counter reach MATCH 2 when counting up Clear CTOUT_4 (pulse fall) 3 0 Counter reach MATCH 0 Limit counter (defines the half period) Int. to update MATCHREL 1/ 2 Change to STATE 1 4 1 Counter reach MATCH 2 when counting down Set CTOUT_5 (pulse rise) 5 1 Counter reach MATCH 1 when counting down Clear CTOUT_5 (pulse fall) 6 1 Counter reach MATCH 3 (0) MATCH 1/ 2 automatic reloading Change to STATE 0 7 1 Counter reach MATCH 3 (0) AND Low value on CTIN_6 Stop counter MATCH 1/ 2 automatic reloading Change to STATE 0 Table 2. Definition of states. Figure 7. State transition diagram. Conclusion The PWM generation carried out by two short pulses shifted in time is a good alternative when isolation and duty-cycles far from 50% are required - specially driving gate charge devices like Mosfet/IGBT. The main advantage over opto-isolated implementations is not necessary create an auxiliary power supply.  Regarding to the architecture, the designer can use microcontrollers equipped with UP/DOWN timers (bidirectional), but is required some external glue logic in order to generate those short pulses. In comparison with the LPC1114 presented solution, the SCT version consumes just one timer/counter. As shown, the SCT peripheral is very independent, resulting in low (or no) MCU intervention after an initial configuration. This simple application used only two inputs, two outputs, two states and eight events. For more complex designs, the SCT provides up to 8 inputs, 16 outputs, 16 events and 32 states. I’ve future plans to make other power electronics applications based on SCT, including a small dot matrix printer controller. Code Red company   provides a tool to draw state diagrams and automatically generate code for the SCT engine, called Red State [2] (not used in this application). Finally, I would like to thank David Donley from NXP, who assisted me by answering my technical enquiries about the State Configurable Timer and suggesting improvements on code. References     [1]    http://www.youtube.com/DirceuRodriguesJr     [2]    http://www.code-red-tech.com/lpcxpresso

This content was originally contributed to lpcware.com by George Romaniuk     This project included testing the performance of the SPIFI interface on LPC4350. Example files were modified to run the M4 core at 200MHz and read and write to SPIFI attached FLASH. Timer was added to measure the execution and data transfer time. Reads were at an amazing 44.9MByte/s; writes were much slower due to FLASH. In addition to SPIFI, some DSP routines were timed and performance was documented.

This content was originally contributed to lpcware.com by Cam Thompson This project is a simple data logging example that takes readings from various sensors, and log the information to a web page. The Cortex-M4 is used to collect and process sample data, and the Cortex-M0 is used to run a web server for supplying data to web clients. This allows data to be viewed on any web browser, including portable devices such as smart phones and tablets. The web data logging example was implemented using the Hitex LPC4300 evaluation board, which has all the necessary components. The LPC43xx has a built-in ethernet controller accessible by either core, and the Hitex evaluation board provides the physical layer. An on-board 128x32 pixel Chip-on-Glass (COG) LCD display, four touch sensors, and several LEDs are used for implementing a simple user interface. The LPC43xx contains a Real-Time Clock (RTC) which is used to record the date and time of data samples.

This content was originally contributed to lpcware.com by Steve Sabram This example project implements acoustic range, finite infinite response (FIR) filters using the LPC4350 demo board and the ARM CMSIS DSP library. A sound resource of a science fiction “zap gun” plays out the headphone jack of the demo board. This sound sample is great for demonstration since it has many low-, mid-, and high-frequency components along the acoustical band. You play the sound resource by touching the capacitive touch buttons on the demo board as explained by the menu shown on the demo board’s LCD. It is best to listen to the sound with a headphone or ear buds. Each of the four buttons plays the same sound resource differently: 1)  Raw – The unprocessed sound plays according to its format (sample rate of 44.1 kHz, 16-bit sample and mono sound). 2)  Low Pass – filtered through a low pass, Butterworth filter with a cutoff of 5 kHz, similar to the bandwidth of a common analog telephone. When played, notice that high pitch components are removed similar       to the sound heard over a telephone. 3)  High Pass – filtered through a high pass, Butterworth filter with a low frequency cutoff of 8 kHz. Notice that the sound is lower in volume since only the upper harmonic components are played. 4)  Backward Mask – The sound resource sample plays in reverse order. The “Zap!” is now a “Zoup!” The digital filters were designed with a favorite public domain tool, WinFilter (http://www.winfilter.20m.com/)       accompanying this example. With exposure of this free DSP design tool via NXP, I hope its author expands its features.

This content was originally contributed to lpcware.com by Brewster LaMacchia   This project shows how to take the filter coefficients created by MDS' QEDesign filter design package and use them for real time audio filtering using the floating point DSP capability of the LPC4350. It's designed to run on the Hitex board and uses the UDA1380 for analog stereo I/O. It also uses the touch buttons, COG LCD, and LEDs for controlling operation.   Keil's Logic Analyzer tool was used for performance measurement. For full details see \doc\gen\html\index.html after unzipping the download.   Updated 16-Mar-12 to correct output rolloff in the UDA1380 due to the deemphasis filter being on by mistake.   Original Attachment has been moved to: MyProj.zip

This content was originally contributed to lpcware.com by Richard Man This project demonstrates how easy it is to port a commonly used open source FatFS code to the LPC4350 using SDIO and built-in SDMMC support. In the competitive embedded microcontroller market, one way a silicon vendor can differentiate its offerings from the rest is by integrating higher-function peripherals onchip. As such, it is no longer unusual to find chips with built-in LCD, USB, CAN, Ethernet, and in some instances, even hardware support for the SD/MMC memory devices. Such is the case with the NXP LPC4350. With two ARM Cortex cores and many other features, it also sports SD/MMC hardware. Without dedicated SD/MMC support, the firmware typically must use bit banging code which is timing sensitive and adds to the complexity of the code.

This content was originally contributed to lpcware.com by Jack Ganssle In this project I looked at the relative performance of the LPC4350's M4 vs. M0 cores, emulating ARM's big.LITTLE approach. In the last few years the industry has increasingly embraced the notion of using multiple processors, often in the form of multicore. Though symmetric multiprocessing – the use of two or more identical cores – has received a lot of media attention, many embedded systems are making use of heterogeneous cores. A recent example is ARM’s big.LITTLE approach, which is specifically targeted to smart phones. A big Cortex-A15 processor does the heavy lifting, but when computational demands are slight it goes to sleep and a more power-frugal A7 runs identical code. NXP’s LPC43xx also has two ARM cores: a capable Cortex-M4 and a smaller M0. Since power constraints are hardly novel to phones, my question was: “if we mirror the big.LITTLE philosophy, what is the difference in performance between the M4 and the M0?”

This content was originally contributed to lpcware.com by Jerry Durand When I found the M4 core in the LPC43xx series could be used as a hardware Floating Point Unit (FPU) while the actual code ran in the M0 core, I immediately thought of an application; a stand-alone 4-axis CNC control box for use with table-top milling machines.  Currently these machines are almost exclusively controlled by software running on very old PC hardware that has a parallel port and either MS-DOS or Windows XP for an operating system. Control of these milling machines entails tasks such as receiving g-code commands in ASCII text and a large amount of high-precision floating point operations which calls for an FPU.  This all has to occur rapidly and continously as each of the 4 motors has to be updated thousands of times per second. It seemed the M0 core would excel at the basic input/output (I/O) and timing functions while using the M4 as an FPU would speed the floating point operations. I originally hoped to port the entire RS274NGC open source Enhanced Machine Controller (EMC) software to the LPC4350 and run it with and without the FPU enabled, comparing the time to process a sample g-code file.  Problems getting the development software and examples set up caused me to run short of time even though NXP was fairly fast to fix problems as they were found.  Instead I modified one of the example programs (GPIO_LedBlinky) to enable testing the performance and this turned out to have some interesting results I might have otherwise missed. I ran the test code in eight different configurations:      1. FPU disabled, 32-bit float multiplication      2. FPU enabled, 32-bit float multiplication      3. FPUdisabled, 64-bit double multiplication      4. FPU enabled, 64-bit double multiplication      5. FPU disabled, 32-bit float division      6. FPU enabled, 32-bit float division      7. FPUdisabled, 64-bit double division      8. FPU enabled, 64-bit double division All tests were run from internal SRAM so external memory access time would not distort the results.  The optimization level was left at the default of zero (0) as I had problems with the compiler eliding parts of my code if I tried higher levels. Test results (loops per second averaged over 10 seconds):      1. 990,550        float, *      2. 2,768,000        FPU, float, *      3. 284,455        double, *      4. 276,796        FPU, double, *      5. 282,316        float, /      6. 1,894,000        FPU, float, /      7. 85,762        double, /      8. 85,053        FPU, double, / As expected 32-bit floating point operations run a lot faster with the FPU, 2.79 times faster for multiply and 6.7 times faster for division.  I would have expected somewhat better performance but this is still a significant improvement in speed. The 64-bit floating point operations were a different story, for both multiplication and division the operations ran SLOWER with the FPU than they do without it.  This points to an error in the library functions since it should be no worse than equal.  I was very surprised by this result and hope when the problem is fixed the 64-bit operations improve significantly. In conclusion the low cost of these parts and the simplicity of using the FPU allows performance improvement to an existing product that uses 32-bit floating point operations.  There is no long development cycle or fear of breaking something in your code as the changes to use the FPU consist of adding a small initilization routine for the FPU and enabling it in your compiler options.  This also leaves open the option of an even greater improvement with no hardware changes once you've had time to port your critical code to run directly on the M4 core instead of just using it as an FPU. In the case of 64-bit floating point operations, it seems this may not be the best choice if you only use the M4 as an FPU.  Running your critical code directly on the M4 may give a significant improvement but that requires porting the code to run on both cores and isn't something I tested.

This content was originally contributed to lpcware.com by Massimo Manca Example application for the "LPC4300 Getting started Kit" to learn and to use the multi processor communication and the newest peripherals of LPC43xx MCU family. System resources used and assignment to the cores: The Cortex-M4 core handles the application logic, manages the 4 touch keys and 4 leds (via the PCA9502 I2C 8 bit I7O expander), the lcd display and the real time clock. The Cortex-M0 core is dedicated to the printer management using the RS232 on board interface (in near future SCT and SGPIO will be used to interface a thermal printing head). The cores communicates using inter processor communication mechanisms minimizing the data passed from M4 to M0 and providing a simple security mechanism.

Description The brushless DC (BLDC) motor control design example describes how to connect and control up to four brushless DC motors using a single NXP microcontroller from the ARM968-based LPC2900 series, making this a low cost solution. Four dedicated motor control PWM blocks keep the CPU load low while running four motors. This allows the microcontroller to still perform other tasks in Hardware used Hitex LPC2939 or LPC2929 evaluation board Hitex BLDC motor control extension board (4x) Interface board Maxon EC32 80W brushless servo motor with Quadrature Encoder Interface (QEI) Three of the Hitex BLDC motor boards are driven as-is (spinning their on-board motors). The fourth board is driving the Maxon EC32 motor using the quadrature encoder interface. The interface board is used to create the correct pin-out that makes it possible to connect the four motor control extension boards to the LPC29xx evaluation board. Block Diagram Documentation BLDC Motor Control Products Below are recommended microcontrollers for use in BLDC motor control applications. Comparison Table Product Pins On-Chip Flash On-Chip RAM Comments LPC2939 208 768KB 56KB Base microcontroller used in the design example. LPC2930 208 0KB 56KB A lower-cost microcontroller with the same amount of pins but without on-chip flash memory. LPC2929 144 768KB 56KB Same on-chip memory as on the LPC2939 but in a smaller package and without USB Host functionality. LPC2927 144 512KB 56KB Same as LPC2929 but with less on-chip flash memory. More Information Image BLDC Motor Control Demo at ESC SV 2009 Schematics LPC2939 Evaluation Board BLDC Motor Control Extension Board Interface Board Example Code BLDC Motor Control Bill of Materials BLDC Motor Controlhttp://www.lpcware.com/sites/default/files/bom.xls Disclaimer This design example shows possible hardware and software techniques used to implement the design. It is imperative that the viewer use sound engineering judgment in determining the fitness of this design example for any particular application. This design example may include information from 3rd parties and/or information which may require further licensing or otherwise. Additional hardware or software design may be required. NXP Semiconductors does not support or warrant this information for any purpose other than an informational design example. lpc2939.eval_.board_.schematics.pdf 143.6 KB documentation.pdf 243.48 KB bldc.board_.schematics.pdf 188.85 KB interface.board_.zip 2 MB example.code_.zip 72.55 KB bom.xls 3.87 KB

Description The Audio Player Design Example, based on an NXP LPC2138 ARM7-based microcontroller, delivers high-quality, uncompressed, 16-bit digital audio playback. This design allows engineers to add MP3 music or sound effects to a variety of consumer applications at a very low cost. Entertaining sounds could be added to children's items or music clips could be easily added to products targeted at teens. There is no limit to the number of existing applications that could be enhanced by inexpensively adding high-quality sound or music. Block Diagram Documentation Audio Player Products Below are recommended microcontrollers for use in implementing this design to a system. Comparison Table Product Pins On-Chip Flash On-Chip RAM Comments LPC2138 64 512KB 32KB Base microcontroller used in the design example. LPC2136 64 256KB 32KB A lower-cost microcontroller with the same amount of on-chip RAM but with only half the on-chip flash memory. LPC2146 64 256KB 32KB + 8KB An upgraded microntroller with more on-chip RAM allowing for a real-time MP3 software decoder. The added USB interface allows file transfer with a personal computer. LPC2148 64 512KB 32KB + 8KB An upgrade to the LPC2138 microntroller, the LPC2148 substitutes Full-speed USB 2.0 device functionality for a slightly higher cost. More Information Images Working Prototype DAC Circuit                                                       SD Card InterfaceSchematics Audio Player Example Code Audio Player Disclaimer This design example shows possible hardware and software techniques used to implement the design. It is imperative that the viewer use sound engineering judgment in determining the fitness of this design example for any particular application. This design example may include information from 3rd parties and/or information which may require further licensing or otherwise. Additional hardware or software design may be required. NXP Semiconductors does not support or warrant this information for any purpose other than an informational design example. documentation.pdf 418.54 KB schematics.zip 123.65 KB example.code_.zip 719.42 KB

Description The Telephone Answering Machine Design Example is a sophisticated telephone answering machine that provides everything commercial devices offer and more. Noteworthy features include improved voice quality and increased storage capacity over commercial machines. Additionally, Internet connectivity enables convenient messaging in the form of SMS messages or e-mails from anywhere in the world. Virtual answering machines can be set up for four different users. A user-friendly interface makes learning how to use this device and taking advantage of its many special features easy for anyone, regardless of their electronics savvy. The highly efficient system is designed around an LPC2138 microcontroller, which features an ARM7 RISC processor. Built with a small handful of components, the Telephone Answering Machine Design Example is cost-effective. The thoughtful inclusion of an external flash memory card and well-chosen algorithms for nearly unlimited storage capacity of crystal-clear messages contribute to the success of the design. Block Diagram Documentation Telephone Answering Machine Products Below are recommended microcontrollers for use in implementing a telephone answering machine. Comparison Table Product Pins On-Chip Flash On-Chip RAM Comments LPC2138 64 512KB 32KB Base microcontroller used in the design example. LPC2136 64 256KB 32KB A lower-cost microcontroller with the same amount of on-chip RAM but with only half the on-chip flash memory. LPC2146 64 256KB 32KB + 8KB An upgraded microcontroller with a USB interface. USB could be used instead of Ethernet to connect to a PC if Internet functionality is not desired. More Information Images Working Prototype Circuit Blocks Answer Flow Telephone Answering Machine Schematics Example Code Bill of Materials Disclaimer This design example shows possible hardware and software techniques used to implement the design. It is imperative that the viewer use sound engineering judgment in determining the fitness of this design example for any particular application. This design example may include information from 3rd parties and/or information which may require further licensing or otherwise. Additional hardware or software design may be required. NXP Semiconductors does not support or warrant this information for any purpose other than an informational design example. documentation.pdf 927.44 KB schematics.pdf 92.13 KB example.code_.zip 646.98 KB bom.txt 1.39 KB

Description This is a demonstration-only design of a Point Of Sale (POS) system using the NXP LPC2214FBD144. Fiscal Cash Register (FCR) is a kind of POS machine which is popularized by governments, in particular, in China. A tax control function is added to the POS machine for revenue supervision. Considering the national standard and function expansion and complexity, an ARM MCU is used in the application market. The LPC2214 is the central control unit of the system. The system consists of an LCD, NAND flash, keypad, printer, RTC, IC card, etc. The FCR demonstration system is divided into two boards. The first is the NXP LPC22xx development board. On this board, general peripheral resources are integrated such as external flash and SRAM, keypad, ethernet, LCD, USB, CF card, and IDE. This can be considered as the motherboard used for the overall application. The FCR-specific resources such as NAND flash, UART, printer, and IC card are on the extended board. If more resources are needed, just replace the extended board. In the system, the LCD module is needed to display the operation and the keypad is used to send commands to the system. NAND flash is used to store the business data and the DOT Matrix printer is used to print the invoice. The IC card is used for security. The POS demo system demonstrates the functions which are important in a complete FCR system. The demo system can be used for software development and can help in reducing the development cycles and time to market. Block Diagram Products Below are recommended microcontrollers for use in implementing this design to a system. More Information Images Working Prototype Point of sale Schematics Example Codehttp://www.lpcware.com/sites/default/files/example.code__3.zip Disclaimer This design example shows possible hardware and software techniques used to implement the design. It is imperative that the viewer use sound engineering judgment in determining the fitness of this design example for any particular application. This design example may include information from 3rd parties and/or information which may require further licensing or otherwise. Additional hardware or software design may be required. NXP Semiconductors does not support or warrant this information for any purpose other than an informational design example. schematics.zip 151.79 KB example.code_.zip 602.53 KB

Description This application provides a human interface via terminal (UART1) menus and numbered selections to select and play audible medical alerts that are generated algorithmically on the NXP LPC23xx. The medical alarms are designed to comply with the IEC 60601-1-8 standard for audible medical alarms. The IEC standard seeks to improve patient safety by standardizing medical audible and visual alarms. The audible portion of the standard specifies high, medium, and low priority alarms, and these are provided via a menu system. In addition, a test menu is added to facilitate analysis of the quality of the alarms generated and their compliance with the standard. Many previous applications used playback techniques to use pre-recorded alarm sounds for the alerts. An algorithmic approach provides a much more efficient, high-quality implementation compared to the pre-recorded sounds. Plus, the sounds can be customized to differentiate equipment while still staying within the parameter limits of the standard. Block Diagram Documentation     IEC Alarm Detailed Documentation Products Below are recommended microcontrollers for use in implementing this design to a system. Comparison Table Product Pins On-Chip Flash On-Chip RAM Comments LPC2364 100 128KB 34KB 128KB flash/34KB RAM version of LPC2368, no SD/MMC LPC2366 100 256KB 58KB 256KB flash version of LPC2368, no SD/MMC LPC2368 100 512KB 58KB + 8KB 100-pin version of LPC2378, no external bus LPC2378 144 512KB 58KB + 8KB 144 pin, similar to LPC2368 but more pins and a MiniBus (8-bit) LPC2387 100 512KB 98KB LPC2368 with 98KB SRAM LPC2388 144 512KB 98KB LPC2378 with 98KB SRAM and USB Host/OTG LPC2458 180 512KB 98KB + 8KB LPC2468 with 16-bit External Memory Interface LPC2460 208 0KB 98KB + 8KB Flashless LPC2468 LPC2468 208 512KB 98KB Host/OTG/device, 32-bit ext. bus, 512KB flash/98KB RAM, 208 pin package LPC2470 208 0KB 98KB + 8KB LPC2460 with XGA LCD controller LPC2478 208 512KB 98KB + 8KB LPC2468 with XGA LCD controller More Information Example Code IEC Alarm Example Code Disclaimer This design example shows possible hardware and software techniques used to implement the design. It is imperative that the viewer use sound engineering judgment in determining the fitness of this design example for any particular application. This design example may include information from 3rd parties and/or information which may require further licensing or otherwise. Additional hardware or software design may be required. NXP Semiconductors does not support or warrant this information for any purpose other than an informational design example. documentation.pdf 395.85 KB example.code_.zip 255.55 KB

Introduction FEZ is an open source development platform for beginners. Powered by an ARM processor (LPC2388) and driven by Microsoft's .NET Micro Framework, FEZ is a doorway to the embedded world. From the ground up, we designed FEZ to be extremely easy to learn. From the boards to the brochures, we made sure to explain everything on your journey. Programming is made easy by using Microsoft's Visual Studio and C#. Enabling those unfamiliar with the embedded world to program without having any prior knowledge. To further assist exploration, we've created an eBook providing extensive details and code examples. Not only is this eBook free, the SDK and IDE are also completely free. This overall low-cost starting point opens the opportunity to learn embedded devices to everyone. Key Features Based on Microsoft's .NET Micro Framework Runs on 72MHz NXP ARM processors (LPC2387 and LPC2388) Supports runtime debugging (breakpoints, variable inspection, stepping, etc.) Use Visual Studio 2008 C# Express Edition for development Advanced capabilities like FAT, USB device, and USB host Easily upgrades to hardware such as Embedded Master Open source hardware design files Use existing shields and holder boards Based on the USBizi chipset (ideal for commercial use) FEZ Mini pin-out compatible with BS2 FEZ Domino pin-out compatible with Arduino Developent Environment FEZ development is done using Visual Studio 2008 C# Express Edition. You're now able to use the same powerful IDE used by PC developers. The benefits of managed C# programming include reducing programming errors significantly and automatically managing system resources. From the code IntelliSense and included peripheral libraries to deploying and debugging applications. These tools are not only the most advanced, they are all free. As you type, IntelliSense gives you the appropriate methods and properties. Stepping through the code on-device allows you to debug problems efficiently. Hardware FEZ comes in two models: FEZ Domino and FEZ Mini. Both include libraries that contain the FAT file system, threading, UART, SPI, I 2 C, GPIO, PWM, ADC, DAC, and many more. Two kits are also available: the starter kit and the robot kit. We also offer a multitude of peripherals for these boards such as Bluetooth, LEDs, buttons, light sensors, and thermometers, to name a few. FEZ Domino FEZ Mini Software Microsoft's .NET Micro Framework is a lightweight implementation of the .NET Framework. It focuses on the specific requirements of resource-constrained embedded systems. Supporting development in C# and debugging on an emulator or the device, both using Visual Studio. The .NET Micro Framework is also open source, released under the Apache 2.0 license and completely free. Developers already experienced with .NET and Visual Studio can take advantage of their skills immediately, reducing the learning curve. The actual C# application development process is completely shielded from the low-level design details of the hardware platform. Combining the benefits with off-the-shelf, low-cost, network-enabled embedded systems creates a rapid product development solution. More Information FEZ Partners Links TinyCLR Brochure TinyCLR Ebook Reference TinyCLR Tutorial Microsoft .NET Micro Framework Blog Wikipedia Fez (hat

DALI Software Development Kit The DALI development kits for LPC are no longer available. The LPC MCUs used are still available. This page is provided for reference purposes only. The DALI Software Development Kit (SDK) for the LPC11xx/LPC13xx contains an updated DALI Library for compliancy with the IEC 62386-102 and IEC 62386-201 standard. Parts of the IEC 62386-207 specification are also included. The DALI slave (AN11174 with OM13026 board) and the USB to DALI master (AN11175 with OM13046 board) can be used in combination with the Windows 7 PC GUI to create a demonstration and evaluation setup as described in UM10553. The SDK contains the example software, DALI library, a hardware description and design files of both boards, documentation and is available for download at the end of this document. DALI Slave OM13026                                                       DALI Master OM13046 System notes Controller side: The LPC1100XL (up to 50 MHz - 45 DMIPS) offers enough performance to integrate DALI message coding/decoding and PWM generation in a single chip Industry-leading low active power consumption of 110 uA/MHz for bus-powered devices Storage of scene settings in non-volatile memory using EEPROM emulation in flash, or integrated EEPROM in LPC11E00 series Up to four 16-bit and 32-bit timers, generating up to 11 PWM signals to control and dim the ballast Reduced development complexity - software can be written in C Reduced bill of materials - significant cost savings through Cortex-M0 architecture, plus many built-in peripherals to interface with lighting drivers and network in LPC1100XL Power stage: LED dimming using the PWM input of the NXP UBA3070 DC-to-DC LED driver with up to 98% efficiency SSL4101 provides mains isolation for both the RGB LED power stage and the DALI wires Low component count and high efficiency through integrated PFC and flyback control functionality GreenChip TEA1721 buck converter supplies LPC1100XL with high efficiency; no-load power consumption levels <10 mW DALI Slave Implementation example (OM13026 board): Contains isolated physical layer for the DALI bus with a Cortex M0 LPC111x microcontroller for the DALI protocol handling, and many I/O functions to steer external lighting drivers for solid state or compact fluorescent lighting applications Schematics, gerbers and BOM also available to speed up development Up to four PWM signals available to independently drive different lighting units Frequency and resolution of the signals is software programmable ON_OFF signal can be used independently from the PWM signals to switch a lighting driver into an OFF or ON state I2C-bus pins can be used to externally connect other devices like EEPROM or a temperature sensor Analog A/D input is available via pin 8 IO signal is left open for the end user UART, I2C and A/D converter functionality not included in the software release

The DMX512 master and slave board (OM13043) are no longer available. This page is provided for reference purposes only. Board information and code is available in the zip file attached to this posting. NXP offers dedicated components to realize DMX512 based systems for both communication and power stages. The reference design provides a basic set of commands (including Remote Device Management) that can be used as a starting point to develop next-generation DMX512 platforms. The DMX512 Software Development Kit (SDK) for the LPC11xx/LPC11Uxx installer contains: AN11153 - Describes the use of the NXP LPC111x Cortex M0 microcontroller to create an RDM enabled DMX512 Slave AN11154 – Describes the use of the NXP LPC11U1x Cortex M0 microcontroller to create a RDM enabled DMX512 Master (USB - DMX interface) UM10536 - Explains how to get started with the NXP DMX512 Master (USB - DMX interface) and DMX512 Slave (demo board for DMX fixture) and the NXP Windows .NET DMX512control application Software Package – DMX master and slave implementation for LPCXpresso toolchain and Windows .NET GUI Schematics, Gerber files and BOM List The SDK is attached to this page (see below) for REFERENCE PURPOSES ONLY. DMX512 Master Board DMX512 Slave Board System notes Controller side: LPC1100XL microcontroller (up to 50 MHz - 45 DMIPS) offers performance needed to integrate DMX message coding/decoding and PWM generation in a single chip Industry-leading low active power consumption of 110 uA/MHz for bus-powered devices Storage of scene settings in non-volatile memory using EEPROM emulation in flash, or integrated EEPROM in LPC11E00 series Up to four 16-bit and 32-bit timers, generating up to 11 PWM signals to control and dim the ballast Reduced development complexity - software can be written in C Reduced bill of materials – significant cost savings through Cortex-M0 architecture, plus many built-in peripherals to interface with lighting drivers and network in LPC1100XL Power stage: LED dimming using the PWM input of the NXP UBA3070 DC-to-DC LED driver with up to 98% efficiency SSL4101 provides mains isolation for both the RGB LED power stage and the DMX wires Low component count and high efficiency through integrated PFC and flyback control functionality GreenChip TEA1721 buck converter supplies LPC1100XL with high efficiency; no-load power consumption levels 10 mW Implementation example (DMX512 slave unit): RDM-enabled DMX512 slave or receiver built around the NXP LPC111x Cortex-M0 microcontroller Features four DMX controllable LEDs, a red heartbeat LED, a green traffic LED, DIP switches for selecting the DMX start address, a 5-position joystick, and an optional LCD The UART and the 16-bit timer/counters of the LPC111x MCU are the main hardware blocks needed The I2C hardware block is used to interface with the (optional) LCD functionality References to DMX512 refer to DMX512-A, since both hardware and software are designed using the latest standard Implementation example (DMX512 master unit): DMX512 controller and monitoring device, built around the NXP LPC11U1x microcontroller, enabling Remote Device Management (RDM) Features a USB interface, a red heartbeat LED, and a green traffic LED The USB and UART of the LPC11U1x MCU are the main hardware blocks needed

The OM13043 kit described below is no longer available (the LPC1227 and LPC1100XL devices are still available). This material is provided for reference materials, but KNX software is still available from Weinzierl Engineering. Building automation systems based on KNX communication protocols Communication is becoming essential in complex buildings. For this reason, NXP cooperates with Weinzierl Engineering to offer dedicated components to realize KNX based systems. A professional version of the KNX system B stack is now available on LPC Microcontrollers to allow a jump start with KNX development. System notes LPC1100XL and LPC1200 series microcontrollers: Based on the highly energy-efficient ARM® Cortex™-M0 processor Dramatically lower the cost per KNX node in home and building automation networks Cortex-M0 architecture ideally suited for low-complexity end nodes Include up to 128 KB Flash and 8 KB SRAM, and offer highly configurable peripherals Can be powered directly from the DC-DC converter of the KNX twisted-pair transceivers, making bus-powered devices easy to implement With performance levels up to 45 DMIPS, a single MCU delivers the resources required to run a KNX System B stack (up to 65535 nodes), with enough bandwidth available for the end application Reduced time to market – full professional stack available from partners with flexible license models A certified implementation of the KNX System B is available for the LPC1200 from Weinzierl Engineering  Implementation example (OM13042 demo board): Available with the NXP LPC1227 microcontroller and ON Semiconductor’s NCN5120 transceiver, suitable for use in KNX twisted pair networks (KNX TP1-256) Specifically designed to simplify design process with a ready-to-implement, energy-efficient KNX TP solution for applications such as lighting switches and control, HVAC control, shutters and occupancy detection Improves power efficiency, reduces development costs, accelerates time to market for KNX applications on ARM Cortex-M0 Application Note AN11231 is available here More information on KNX:  www.knx.org KNX TP Stack System B from Weinzierl Engineering - The new dimension of KNX development Each KNX device is based on a device model, that specifies both the management procedure (that is, how the device is configured via the bus) and identifies the resources available to the device (for example, the maximum size of the connection table). System B (mask version 07B0) is a new device model that has been defined specifically for the implementation of complex KNX devices. The main advantage lies in the number of available communication objects. While previous devices models were limited to 255 objects or less, System B theoretically permits up to 65,535 communication objects. To achieve this, the formats of the communication tables (group address, association and group object tables) have been redefined in the KNX specification for System B. System B devices can update their communication objects at system startup. This function is called Read-On-Init and can be activated individually for each object. Once the application is started the system software sends group read-value services independent from the application task. These services are scheduled by the stack to ensure that the bus is not excessively loaded at startup. System B also offers a greatly increased address space. The configuration data (application, parameters and tables) can be loaded into a range of up to 1 MB (20-bit addressing) via the bus (using memory services). To access system parameters, additional properties in the interface objects of the system have been introduced. System B is supported by the ETS manufacturer tool MT4, by ETS3 andETS4. Implementation for optimal performance Weinzierl Engineering as a KNX system supplier offers a new implementation for KNX System B, specifically targeted at complex devices with a 32-bit architecture like the Cortex M0 from NXP. It includes a complete implementation of the specification and is optimized to ensure high performance for all application sizes. A major consideration in the development of System B is the timely (real-time) processing of the large association table, which contains the assignment of group addresses to the communication objects and vice versa. It is loaded by ETS and is not sorted. For a table length of more than a thousand entries, linear search algorithms are not effective and therefore additional look-up tables have been introduced that allow quick access via indices. The processing of the communication objects has also been accelerated and a linear search through all objects is avoided with the use of additional buffers. Although these design features may require additional memory, they facilitate low CPU clock speeds. Higher performance is achieved at the same frequency with than with previous implementations with considerably reduced KNX resources. The System B implementation from Weinzierl Engineering uses a virtual address space that is resolved at the driver level and mapped to the corresponding physical storage areas. This means that applications are easily ported to different platforms. As for all Weinzierl's stack implementations, the focus is to ensure ease of application development. The application interface has been largely maintained and is accessible via comprehensive API functions. It is possible to implement either internal or external applications. An internal application is bundled together with the stack in the device and the ETS simply has to load the parameters and tables, which ensures quick download times. An external application is loaded by the ETS along with the parameters and tables. The stack also supports additional interface objects (user properties). These objects can be used, for example, to set device parameters using point-to-point communication on the bus. ETS parameters can also be realized with Properties. For the creation of the product data base with ETS MT4 (Manufacturer Tool) our bus monitor and KNX development tool Net'n Node has been extended with a new export function. After importing the data of the software project it directly generates an XML file that contains all the storage areas, load controls and binary application data. This XML file can be imported directly into the MT4 solution.

Welcome to the LPC4350 Hitex Board Getting Started Guide! This page will walk new owners of the LPC4350 development platform from Hitex through bringing the board up with the example projects. Connecting the Hardware Here is a photo of a typical hardware setup. The board is connected to a PC through a JTAG debugging interface and a USB-serial cable. +5V center-positive power is also applied to X14. If a 5V regulated power supply is not available, the board may be powered by USB connected to one of the USB connectors using the included cable. To date we have tested this board with a Keil ULink 2, ULink Pro, and the Segger JLink but any JTAG-capable tool should be able to debug with the LPC4350. The example projects should run without modification on Keil MDK. To see the debugging output from the example code on the serial-to-usb cable, first the driver must be installed. Many cables use chips from FDTI and the drivers can be downloaded from here: FDTI VCP Drivers. To view the serial output, any standard terminal program such as Tera Term can be used. LPC4300 Hitex Board with Connections LPC4350 PDL Examples and Flash Drivers The example code for this board can be downloaded from here: LPC4350 PDL There are 53 code examples. Once the code has been downloaded, it should be unzipped. The unzipped peripheral driver library includes an Examples directory containing examples that work with each peripheral on the LPC4350 dual-core microcontroller. Also included are flash drivers located in the Tools\Flash\Keil_Binaries directory. If using ARM/Keil MDK V4.22 and earlier, these should be copied to the C:\Keil\ARM\Flash directory. Later tool versions should include these drivers. LPC4350 PDL Examples and Flash Drivers If you are using the Hitex LPC4350 board using the ARM/Keil MDK, the driver library projects have several configurations built-in. They can build for Internal SRAM, build for SPIFI (external 1 MB QSPI flash on the Hitex board), or build for Hitex Flash (external parallel flash on the Hitex board).The best performance will be achieved with building for Internal SRAM, but if you would like the board to boot on its own without a debugger, then the code will have to be built either for SPIFI or for Hitex Flash. LPC4350 PDL Keil Project Configurations LPC4350 PDL Boot Jumpers Once you have successfully programmed the flash on the Hitex board, there is one step left before the LPC4350 can boot from external flash. That final step is to configure the boot mode using the boot mode jumpers. LPC4350 PDL Boot Jumpers Here is a diagram that shows how to configure the boot jumpers on the LPC4350 Hitex board. The boards are shipped with the center two positions shorted with jumpers. This configures the LPC4350 to boot from the "EMC" (External Memory Controller) which is connected to the parallel flash on the Hitex board. When using the sample projects with the Keil tool, after building a project, the LOAD button can be used to program it into Flash memory for stand-alone booting. To debug a project that has been programed in to Flash, you may need to click the LOAD button to configure the memory controller on the LPC4350 (if it has been reset) before entering debug mode. LPC4350 PDL Boot Jumper Diagram We can ship boards with two example projects flashed in them- one loads when the board is configured to boot from Parallel Flash, and a second loads when the board is configured to boot from QSPI flash. Recent boards are shipped with a Mass Storage Class ROM USB demo in parallel Flash and an LED/button demo in QSPI Flash. Using the SD/MMC Card Slot The SD/MMC Card Slot, on the right edge of the board in the photo above, can accept an SD card to read and write data. Before this slot will work properly, several jumpers must be configured on the Hitex board. The jumpers needed are: Jumper Block Jumper Settings SV3 positions 7-8 and 13-4 must be open SV6 positions 1-2, 3-4, 7-8, 15-16, 17-18 must be open SV12 all positions must be shorted JP9 position 1-2 must be shorted Next- load the Usb_MassStorage example from the USBDEV_ROM directory. This Mass Storage Class example has been extended with sdio drivers. Insert an SD card (we have tested 2GB) into the SD connector on the right side of the board. Connect X2 (USB1, high-speed) to a PC. You should see a disk drive on the PC and be able to read and write the SD card. Operation at 204 MHz The LPC4350 is qualified to operate at up to 204 MHz, but normally starts up at a slower speed to make design easier. In particular, even if memories and power subsystems are not designed to support 204 MHz, booting is still possible. To run the LPC4350 at 204 MHz, take a look at the BOOTFAST example project. This project supports the same configurations (SRAM, Parallel Flash, and QSPI Flash) as the other examples, but after startup, it relocates some code to internal SRAM, and then it reconfigures the parallel flash and SPIFI peripheral to a high speed mode and increases the clock speed to 204 MHz. This is a good way to see how a standard system would boot. Typically, the most critical code would also be located within internal SRAM which runs at 204 MHz with zero wait states while other less performance-intensive code could be located in external Flash, SRAM, or QSPI flash which are set up to run at 102 MHz in this example. Multi-Core Operation The LPC4350 contains two cores, a Cortex-M4 and a Cortex-M0 which both operate at 204 MHz. An example that demonstrates how you can use the cores together is located in Examples\DUALCORE\Mbx_Demo. This example sets up a mailbox mechanism to facilitate communication between the two cores. The M0 core is assigned the task of outputting serial communications via UART 1. This example includes a multi-project workspace. Once the workspace is opened, the M0 project must be built first before the M4 project can be built. For more details, see the abstract in the M4 project. State Configurable Timer (SCT) The LPC4350 contains a special timer called the State Configurable Timer (SCT). The SCT is a timer with a state machine integrated into it. It is great for doing complex signal generation such as PWM waveforms. An SCT example is provided in the LPC4350 code repository which emulates the behavior of a simple traffic light. The example is called SCT_TrafficLight and is in the SCT subdirectory of the Examples directory in the code bundle. To use this example, you must assemble a PCB with four LEDs and two pushbuttons. Here is a photo of an example board: SCT Traffic Light SCT Traffic Light Schematic The traffic light should be connected as follows: Signal Port Connector Signal Wire Color CTOUT_0 P4_2 X11, pin 7 Red LED red CTOUT_1 P4_1 JP20, pin 2 Yellow LED yellow CTOUT_2 P4_4 JP22, pin 2 Green LED green CTOUT_3 P4_3 X11, pin 6 White LED red CTIN_2 P4_10 X11, pin 13 WALK Button blue CTIN_3 P7_3 SV18, pin 16 RESET button yellow GND ADC ADC, GND Common black Traffic Light Connections If you would like to edit the state machine used in the traffic light example, you will need to use the LPCXpresso or Red Suite tool, which has "Red State," a state-machine editor, built-in. Here is an image of the state machine used in the traffic light example: Traffic Light Diagram Once you have edited the state machine, click "Generate Code." You can test the state machine within LPCXpresso if you have a Red Probe or an LPC-Link probe, or you can copy the following source code files from the LPCXpresso project over to the Keil SCT project: sct_fsm.c, sct_fsm.h, and sct_user.h and make use of a JLink or uLink. Serial GPIO (SGPIO) The LPC4350 contains a peripheral called Serial GPIO which is similar to a bank of shift registers with some extra logic for bonding and counters for timing. The SGPIO is great for implementing standard or custom digital data interfaces. To demo this peripheral, we have configured it to implement four I2S ports to add 7.1 8-speaker audio capability to the LPC4300 family. The example for this will soon be provided in the LPC4350 code repository. The example will be called SGPIO_71 and will be in the SGPIO subdirectory of the Examples directory in the code bundle. To use this example, you need a demonstration PCB with four stereo audio codecs on board. Here is a photo of an example board: LPC4350 Codec Board The codec board should be connected as follows: Signal Connector Wire Color MCLK SV16, pin 6 blue LRCLK SV3, pin 11 green SCLK SV5, pin 6 yellow GND GND post near U23 black V33 JP5, pin 2 red - - - SDIN0 SV13, pin 4 blue SDIN1 SV5, pin 4 green SDIN2 SV16, pin 4 yellow SDIN3 SV3, pin 3 blue LPC4300 Hitex Codec Connections Once you have connected the codec board, you should be able to connect the Hitex board to your PC using a USB cable to connector X2. After running the example project, a stereo USB speaker device should appear on your PC which can accept audio and mirror it onto two of the stereo audio channels.