Which Cortex-M CPU revision is implemented in NXP microcontrollers?

[lpcware-support]

CPU Core Revision

Background

The CPU core revision level is identified in the System Control Block (SCB) by the CPUID register found at address 0xE000ED00.  Further information can be found in ARM’s Device Generic User Guide.

ARM defines the structure of this register for each CPU variant.

Cortex-M0:       http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/Bhccjgga.html

Cortex-M0+:     http://infocenter.arm.com/help/topic/com.arm.doc.ddi0484c/Bhccjgga.html

Cortex-M3:       http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/CIHFDJCA.html

Cortex-M4:       http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/CIHCAGHH.html

Reference

The following devices are provided for reference.

                LPC812                 r0p0       Cortex-M0+

                LPC1768               r2p0       Cortex-M3

                LPC1788               r2p0       Cortex-M3

                LPC1837               r2p1       Cortex-M3

                LPC1850               r2p1       Cortex-M3

                LPC4357               r0p1       Cortex-M4F

Debugging

When debugging under the Keil uVision IDE, enterring "SCB" in the Memory1 view will display the contents of the CPUID register.