how to do 16bit flexio spi transfers with ksdk2?

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how to do 16bit flexio spi transfers with ksdk2?

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robotjosh
Contributor IV

I'm trying to get 16bit flexio spi to work on a frdm-k82 with ksdk2.  I started with the ksdk demo for flexio spi and removed the slave stuff.  The default options for 8bit flexio spi work as expected.  Tried changing the parameters transfer config flags to kFLEXIO_SPI_16bitMsb and/or master config dataMode to kFLEXIO_SPI_16BitMode.  All 3 combinations of options result in nothing happening when a transfer is started.  None of the functions are failing an assert or returning non-zero status bytes, it just never does anything on the spi bus and the complete callback is never called.  I'm not too familiar with how flexio works but it looks like its setting up edma with 2 minor loops, each configured for 16bits, but the source offset is only incremented by 1 so I'm not sure what its trying to do.  I could dig into the flexio docs and debug this or maybe theres a setting I'm not setting up right?

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robotjosh
Contributor IV

Hi Rong-

Looks like you have only modified 2 flags for 16bit operation.  Have you tested this code?  I was not able to observe 16bit transfers changing either flag.

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Josh,

I have modified two lines, how about using the following code?

BR

XiangJun Rong

int main(void)

{

    BOARD_InitPins();

    BOARD_BootClockRUN();

    BOARD_InitDebugConsole();

    CLOCK_SetFlexio0Clock(1U);

    PRINTF("FLEXIO Master edma - DSPI Slave interrupt example start.\r\n");

    PRINTF("This example use one flexio spi as master and one dspi instance as slave on one board.\r\n");

    PRINTF("Master uses edma and slave uses interrupt way.\r\n");

    PRINTF("Please make sure you make the correct line connection. Basically, the connection is:\r\n");

    PRINTF("FLEXIO_SPI_master -- DSPI_slave   \r\n");

    PRINTF("   CLK      --    CLK  \r\n");

    PRINTF("   PCS      --    PCS  \r\n");

    PRINTF("   SOUT     --    SIN  \r\n");

    PRINTF("   SIN      --    SOUT \r\n");

    uint32_t errorCount;

    uint32_t i;

    flexio_spi_master_config_t masterConfig;

    dspi_slave_config_t slaveConfig;

    flexio_spi_transfer_t masterXfer;

    dspi_transfer_t slaveXfer;

    dma_request_source_t dma_request_source_tx;

    dma_request_source_t dma_request_source_rx;

    /* Master config */

    /*

     * masterConfig.enableMaster = true;

     * masterConfig.enableInDoze = false;

     * masterConfig.enableInDebug = true;

     * masterConfig.enableFastAccess = false;

     * masterConfig.baudRate_Bps = 500000U;

     * masterConfig.phase = kFLEXIO_SPI_ClockPhaseFirstEdge;

     * masterConfig.dataMode = kFLEXIO_SPI_16BitMode; //kFLEXIO_SPI_8BitMode;

     */

    //Rong Wrote

    masterConfig.dataMode = kFLEXIO_SPI_16BitMode; //kFLEXIO_SPI_8BitMode;

    //Rong wrote end

    FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig);

    masterConfig.baudRate_Bps = 500000U;

    spiDev.flexioBase = BOARD_FLEXIO_BASE;

    spiDev.SDOPinIndex = FLEXIO_SPI_SOUT_PIN;

    spiDev.SDIPinIndex = FLEXIO_SPI_SIN_PIN;

    spiDev.SCKPinIndex = FLEXIO_SPI_CLK_PIN;

    spiDev.CSnPinIndex = FLEXIO_SPI_PCS_PIN;

    spiDev.shifterIndex[0] = 0U;

    spiDev.shifterIndex[1] = 1U;

    spiDev.timerIndex[0] = 0U;

    spiDev.timerIndex[1] = 1U;

    FLEXIO_SPI_MasterInit(&spiDev, &masterConfig, FLEXIO_CLOCK_FREQUENCY);

    /* Slave config */

    slaveConfig.whichCtar = kDSPI_Ctar0;

    slaveConfig.ctarConfig.bitsPerFrame = 8;

    slaveConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;

    slaveConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;

    slaveConfig.enableContinuousSCK = false;

    slaveConfig.enableRxFifoOverWrite = false;

    slaveConfig.enableModifiedTimingFormat = false;

    slaveConfig.samplePoint = kDSPI_SckToSin0Clock;

    DSPI_SlaveInit(BOARD_DSPI_SLAVE_BASE, &slaveConfig);

    /* Set dspi slave interrupt priority higher. */

    NVIC_SetPriority(MASTER_SPI_IRQ, 1U);

    NVIC_SetPriority(SLAVE_SPI_IRQ, 0U);

    /* Set up the transfer data */

    for (i = 0U; i < TRANSFER_SIZE; i++)

    {

        masterTxData[i] = i % 256U;

        masterRxData[i] = 0U;

        slaveTxData[i] = ~masterTxData[i];

        slaveRxData[i] = 0U;

    }

    isTransferCompleted = false;

    /* Set up slave first */

    DSPI_SlaveTransferCreateHandle(BOARD_DSPI_SLAVE_BASE, &g_s_handle, DSPI_SlaveUserCallback, NULL);

    /*Set slave transfer ready to receive/send data*/

    slaveXfer.txData = slaveTxData;

    slaveXfer.rxData = slaveRxData;

    slaveXfer.dataSize = TRANSFER_SIZE;

    slaveXfer.configFlags = kDSPI_SlaveCtar0;

    DSPI_SlaveTransferNonBlocking(BOARD_DSPI_SLAVE_BASE, &g_s_handle, &slaveXfer);

    /*Init DMA for example.*/

    DMAMGR_Init();

    dma_request_source_tx = (dma_request_source_t)(FLEXIO_DMA_REQUEST_BASE + spiDev.shifterIndex[0]);

    dma_request_source_rx = (dma_request_source_t)(FLEXIO_DMA_REQUEST_BASE + spiDev.shifterIndex[1]);

    /* Request DMA channels for TX & RX. */

    if (dma_request_source_tx < 0x200)

    {

        DMAMGR_RequestChannel((dma_request_source_t)dma_request_source_tx, 0, &txHandle);

        DMAMGR_RequestChannel((dma_request_source_t)dma_request_source_rx, 1, &rxHandle);

    }

    else

    {

        DMAMGR_RequestChannel((dma_request_source_t)dma_request_source_tx, 16, &txHandle);

        DMAMGR_RequestChannel((dma_request_source_t)dma_request_source_rx, 17, &rxHandle);

    }

    /* Set up master transfer */

    FLEXIO_SPI_MasterTransferCreateHandleEDMA(&spiDev, &g_m_handle, FLEXIO_SPI_MasterUserCallback, NULL, &txHandle,

                                              &rxHandle);

    /*Start master transfer*/

    masterXfer.txData = masterTxData;

    masterXfer.rxData = masterRxData;

    masterXfer.dataSize = TRANSFER_SIZE;

    //Rong wrote

   // masterXfer.flags = kFLEXIO_SPI_8bitMsb;

    masterXfer.flags=kFLEXIO_SPI_16bitMsb;

    //Rong wrote end

    FLEXIO_SPI_MasterTransferEDMA(&spiDev, &g_m_handle, &masterXfer);

    /* Wait slave received all data. */

    while (!isTransferCompleted)

    {

    }

    errorCount = 0U;

    for (i = 0U; i < TRANSFER_SIZE; i++)

    {

        if (masterTxData[i] != slaveRxData[i])

        {

            errorCount++;

        }

        if (slaveTxData[i] != masterRxData[i])

        {

            errorCount++;

        }

    }

    if (errorCount == 0U)

    {

        PRINTF("FLEXIO SPI master <-> DSPI slave transfer all data matched!\r\n");

    }

    else

    {

        PRINTF("Error occured in FLEXIO SPI master <-> DSPI slave transfer!\r\n");

    }

    FLEXIO_SPI_MasterDeinit(&spiDev);

    DSPI_Deinit(BOARD_DSPI_SLAVE_BASE);

    while (1)

    {

    }

}

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