Kinetis K65 PEE mode with KSDK 2.0

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Kinetis K65 PEE mode with KSDK 2.0

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darnaiadam
Contributor III

Hy everyone!

My problem is that I'd like to switch the clock mode from the default FEI mode to PEE mode in order to use an external, 16 MHz crystal, and reach the needed 120 MHz frequency. I configured the MCG correctly, but it seems the processor can't switch to PEE mode. Here is my code:

#define XTAL0_CLK_HZ (16000000U)

/* Multiple-purpose Clock Generator configuration structure */
static const mcg_config_t mcg_conf =
{
        /* At the end of clock configuration, the aimed MCG mode is PEE. It's process starts from the reset state (FEI), and go through FBE, PBE, than PEE. */
        .mcgMode = kMCG_ModePEE,
        /* IRCLKEN is disabled */
        .irclkEnableMode = 0x0U,
        /* Set IRC to slow */
        .ircs = kMCG_IrcSlow,
        /* IRC divider factor */
        .fcrdiv = 0x01/*0x0U*/,
        /* FLL Clock divider. OxO means OSC Clock divided by 32. */
        .frdiv = 0x0,
        /* Oscillator selector */
        .oscsel = kMCG_OscselOsc,
        .pll0Config =
        {
                /* PLL0 enabled independent */
                .enableMode = 0x0U,
                /* OSC clock divided by 2 */
                .prdiv = 0x1U,
                /* The taken value multiplied by 30. The result clock is (16_000_000 / 2) * 30 = 240 MHz. */
                .vdiv = 0xEU,
        },
        .pllcs = kMCG_PllClkSelPll0,
};

/* System Integration Module configuration structure */
static const sim_clock_config_t simConfig =
{
        /* Selects FLL */
        .pllFllSel = 0U,
        .pllFllDiv = 0U,
        .pllFllFrac = 0U,
        .er32kSrc = 0U,
        /* OUTDIV1: 0x0U, MCGOUTCLK is divided by 1 for Core Clock (120 MHz)
         * OUTDIV2: 0x1U, MCGOUTCLK is divided by 2 for Bus Clock (60 MHz)
         * OUTDIV3: 0x1U, MCGOUTCLK is divided by 1 for FlexBus Clock (60 MHz)
         * OUTDIV4: 0x4U, MCGOUTCLK is divided by 5 for flash clock (24 MHz) */
        .clkdiv1 = 0x1140000U,
};

/* OSC configuration structure */
static const osc_config_t osc_conf =
{
        /* Using oscillator with external 16 MHz crystal */
        .freq = XTAL0_CLK_HZ,
        .capLoad = 0x0U,
        /* work mode is in High Gain */
        .workMode = kOSC_ModeOscHighGain,
        /* External clock is disabled */
        .oscerConfig =
        {
                .enableMode = 0x0U,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
                .erclkDiv = 0x0U,
#endif
        },
};

void clock_init(void)
{
    /* external OSC0, 16MHz, desired freq is 120 MHz */

    CLOCK_SetSimSafeDivs();

    CLOCK_InitOsc0(&osc_conf);

    CLOCK_SetXtal0Freq((uint32_t)XTAL0_CLK_HZ);

    MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(mcg_conf.frdiv));

    CLOCK_BootToPeeMode(mcg_conf.oscsel,mcg_conf.pllcs,&mcg_conf.pll0Config);

    CLOCK_SetSimConfig(&simConfig);

    SystemCoreClock = 120000000U;

    SystemCoreClockUpdate();
}

What should I modify to make it run? I generated a code, using Clock Tool, but the result is the same. This code can only be good if I change the .workMode from kOSC_ModeOscHighGain to kOSC_ModeOscLowPower.

1 Solution
175 Views
jingpan
NXP TechSupport
NXP TechSupport

Hi Darnai,

In low power mode, the amplitude of the clock wave is around 1.6v. It consumes less power than high-gain mode. In high-gain mode, the amplitude of the clock wave is around 3v. So it is less susceptible than low-power mode.

Regards,

Jing

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3 Replies
175 Views
jingpan
NXP TechSupport
NXP TechSupport

Hi Darnai,

Please use SDK_2.2_TWR-K65F180M\boards\twrk65f180m\driver_examples\lptmr for example. This case use external 16M oscillator, PEE mode and cpu run at 120M. This case also set kOSC_ModeOscLowPower which sets MCG_C2->EREFS. This bit tell the system to use oscillator. If you dont set this bit, system will use external reference clock as the clock source. As to the kOSC_ModeOscHighGain, it not only set EREFS bit, but also HGO bit. If you set this bit, you should use an external feedback resistor. Please look at figure 28-4 in reference manual.

Regards,

Jing

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darnaiadam
Contributor III

Hi Jing!

Thank you for your respond, the problem was what you wrote. I should use a feedback resistor in high gain mode. I thought that the whole processor works in low power mode when I choose that mode. I couldn't clarify what low power and high gain mode mean.

Best regards,

Adam

0 Kudos
176 Views
jingpan
NXP TechSupport
NXP TechSupport

Hi Darnai,

In low power mode, the amplitude of the clock wave is around 1.6v. It consumes less power than high-gain mode. In high-gain mode, the amplitude of the clock wave is around 3v. So it is less susceptible than low-power mode.

Regards,

Jing

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