KV5x HSADC CTRL2 DIVA doesn't do anything?

[gregoryw]

Hi everyone,

I'm trying to control the sampling rate of the 12-bit ADC by using the SDK2 driver.

I used the clock driver to set the system clock to 237.5MHz based on a 25MHz TCXO.

Right now I'm modifying the struct as follows:

hsadcConverterConfigStruct.clockDivisor = 3U;

And writing the registers using:

HSADC_SetConverterConfig(DEMO_HSADC_INSTANCE, kHSADC_ConverterA | kHSADC_ConverterB, &hsadcConverterConfigStruct);

I'm also toggling an LED to measure the acquisition speed.

It seems that no matter what value I use (in range, 3-64), the acquisition speed doesn't change.

Here is the whole block of code:

hsadc_config_t hsadcConfigStruct;
hsadc_converter_config_t hsadcConverterConfigStruct;
hsadc_sample_config_t hsadcSampleConfigStruct;

HSADC_GetDefaultConfig(&hsadcConfigStruct);
hsadcConfigStruct.dualConverterScanMode = kHSADC_DualConverterWorkAsTriggeredParallel;
hsadcConfigStruct.DMATriggerSoruce = kHSADC_DMATriggerSourceAsSampleReady;
HSADC_Init(DEMO_HSADC_INSTANCE, &hsadcConfigStruct);
HSADC0->CTRL1 |= HSADC_CTRL1_DMAENA(1);
/* Configure each converter. */
HSADC_GetDefaultConverterConfig(&hsadcConverterConfigStruct);

hsadcConverterConfigStruct.clockDivisor = 3U;
/* Enable the calibration in power up period. */
//hsadcConverterConfigStruct.powerUpCalibrationModeMask =
// (kHSADC_CalibrationModeSingleEnded | kHSADC_CalibrationModeDifferential);
HSADC_SetConverterConfig(DEMO_HSADC_INSTANCE, kHSADC_ConverterA | kHSADC_ConverterB, &hsadcConverterConfigStruct);
/* Enable the power for each converter. */
HSADC_EnableConverterPower(DEMO_HSADC_INSTANCE, kHSADC_ConverterA | kHSADC_ConverterB, true);
while (
(kHSADC_ConverterAPowerDownFlag | kHSADC_ConverterBPowerDownFlag) ==
((kHSADC_ConverterAPowerDownFlag | kHSADC_ConverterBPowerDownFlag) & HSADC_GetStatusFlags(DEMO_HSADC_INSTANCE)))
{
}
/* Wait the calibration process complete. None End of Scan flag will be set after power up calibration process. */
//while ((kHSADC_ConverterAEndOfCalibrationFlag | kHSADC_ConverterBEndOfCalibrationFlag) !=
// ((kHSADC_ConverterAEndOfCalibrationFlag | kHSADC_ConverterBEndOfCalibrationFlag) &
// HSADC_GetStatusFlags(DEMO_HSADC_INSTANCE)))
//{
//}
//HSADC_ClearStatusFlags(DEMO_HSADC_INSTANCE,
// (kHSADC_ConverterAEndOfCalibrationFlag | kHSADC_ConverterBEndOfCalibrationFlag));
/* Make each converter exit stop mode. */
HSADC_EnableConverter(DEMO_HSADC_INSTANCE, kHSADC_ConverterA | kHSADC_ConverterB, true);

/* Configure the samples. */
HSADC_GetDefaultSampleConfig(&hsadcSampleConfigStruct);
/* For converter A. */
hsadcSampleConfigStruct.channelNumber = DEMO_HSADC_CONVA_CHN_NUM1;
hsadcSampleConfigStruct.channel67MuxNumber = DEMO_HSADC_CONVA_CHN67_MUX_NUM1;
hsadcSampleConfigStruct.enableDifferentialPair = DEMO_HSADC_CONVA_CHN_NUM1_ENABLE_DIFF;
HSADC_SetSampleConfig(DEMO_HSADC_INSTANCE, 0U, &hsadcSampleConfigStruct);
hsadcSampleConfigStruct.channelNumber = DEMO_HSADC_CONVA_CHN_NUM2;
hsadcSampleConfigStruct.channel67MuxNumber = DEMO_HSADC_CONVA_CHN67_MUX_NUM2;
hsadcSampleConfigStruct.enableDifferentialPair = DEMO_HSADC_CONVA_CHN_NUM2_ENABLE_DIFF;
HSADC_SetSampleConfig(DEMO_HSADC_INSTANCE, 1U, &hsadcSampleConfigStruct);
/* For converter B.
* In HSADC_SetSampleConfig(), the channel number 0~7 represents input 0~7 of converter A and channel number 8~15
* represents input 0~7 of converter B.
*/
hsadcSampleConfigStruct.channelNumber = (DEMO_HSADC_CONVB_CHN_NUM1 + 8U);
hsadcSampleConfigStruct.channel67MuxNumber = DEMO_HSADC_CONVB_CHN67_MUX_NUM1;
hsadcSampleConfigStruct.enableDifferentialPair = DEMO_HSADC_CONVB_CHN_NUM1_ENABLE_DIFF;
HSADC_SetSampleConfig(DEMO_HSADC_INSTANCE, 8U, &hsadcSampleConfigStruct);
hsadcSampleConfigStruct.channelNumber = (DEMO_HSADC_CONVB_CHN_NUM2 + 8U);
hsadcSampleConfigStruct.channel67MuxNumber = DEMO_HSADC_CONVB_CHN67_MUX_NUM2;
hsadcSampleConfigStruct.enableDifferentialPair = DEMO_HSADC_CONVB_CHN_NUM2_ENABLE_DIFF;
HSADC_SetSampleConfig(DEMO_HSADC_INSTANCE, 9U, &hsadcSampleConfigStruct);
/* Enable the sample slot.
* The conversion sequence for converter A includes sample slot 0 and 1, while the sequence for converter B
* includes sample slot 8 and 9. Sample slot 0~7 can reference only to converter A and sample slot 8~15 can
* reference only to converter B in parallel mode.
*/
sampleMask = HSADC_SAMPLE_MASK(0U) /* For converter A. */
| HSADC_SAMPLE_MASK(1U) /* For converter A. */
| HSADC_SAMPLE_MASK(8U) /* For converter B. */
| HSADC_SAMPLE_MASK(9U); /* For converter B. */

HSADC_EnableSample(DEMO_HSADC_INSTANCE, sampleMask, true);
HSADC_EnableSample(DEMO_HSADC_INSTANCE, (uint16_t)(~sampleMask), false); /* Disable other sample slots. */

Not sure what I'm doing wrong here.

[chris_brown]

Hi gregoryw‌,

I know it has been sometime since this thread was commented on but I was just made aware of it.  

There have been no issues reported with DIVA during validation of this device, so I can't imagine it doesn't work.  You might want to check and verify that your DMA is properly waiting on new triggers from the HSADC.  If misconfigured, the DMA could simply perform 1024 transfers successively without waiting on the HSADC.  It might not then matter how the HSADC is configured.  

Regards,

Chris 

[xiangjun_rong]

Hi,

Regarding your remark "Is SAMPTIM a viable method of controlling the sampling rate?", as you know that there is sample/hold device for any ADC converter, the SAMPTIM can controls the sample/hold time, i do not think it is the same concept for the sampling cycle time for example 5MSPS(million samples per second).

But from theory, both the DIVA and SAMPTIMA can take effect on the sampling rate if you use continuous software triggering.

Hope it can help you.

[xiangjun_rong]

Hi, Wang,

For the cyclic ADC converter of KV58, if you do want to test the sampling time of ADC converter, I suggest you use continuous mode and use polling mode, because I suspect that the KV58 is not fast enough to handle interrupt of ADC. After the conversion is over, toggle GPIO.

Generally, we use external triggering signal to trigger ADC converter, and use interrupt mechanism to read sample data, in the case, it does not matter for the ADC clock frequency. You can set the ADC clock as 80MHz from system clock via DIVA in HSADCx_CTRL2 register.

Hope it can help you

BR

XiangJun Rong

[gregoryw]

Thank you for your input.

As you can see in my code, I am setting DIVA using the fsl_clock driver in SDK2.

I have the DMA controller sending an interrupt every 1024 samples.

I write to PTOR every interrupt.

Using a scope, my toggle rate was 2.899KHz for 1024 samples. This roughly translates to 5.937 megasamples/second.

I could try a direct write to DIVA I suppose...

Is SAMPTIM a viable method of controlling the sampling rate?

[xiangjun_rong]

Hi, Wong,

I am sorry, I am unclear about your purpose of the test code, do you want to test the performance of the high speed ADC or you just want to sample one or multiple ADC channels with a fixed sampling rate. If you want to sample one or multiple channels in a fixed rate, as you know that you can NOT use the DIVA in HSADCx_CTRL2 register to control the sampling rate. For example, you want to sample one channel in 1Khz, I suggest you use PIT to generate the 1KHz triggering signal and use crossbar to route the signal to HSADC0A_SYNC(XBARA_OUT12), in this way, you can get 1Khz sampling rate.

For detailed inf, pls refer to 29.1.2 XBARA signal output assignment in RM of KV58.

If you do want to test the ADC performance, I will continue.

BR

Xiangjun Rong

[gregoryw]

Thank you for suggesting the PIT, I will look in to it.

Right now, I'm verifying the sampling rate by using a DMA channel which copies the RSLT[0] register to memory, and has a major interrupt every 1024 samples. The DMA is triggered by the RDY status, and the DMA interrupt routine toggles an LED.

In the above scheme, I believe the HSADC clock is directly responsible for the sample rate.

No matter what value I change DIVA to, the toggle rate of that LED doesn't change. To me, this implies that the clock rate of the HSADC is not affected by my attempts to change the value of DIVA.

I simply would like to make sure that the HSADC is not being overclocked and I would like physical proof.