I'm porting a firmware running on a custom board from KSDK 1.3 to KSDK 2.1. I use Kinetis MK64FN1M0VLQ12 clocked with a 12.288 MHz crystal. With KSDK 1.3 the firmware works fine. With KSDK 2.1 I am not able to correctly setup clock.
void BOARD_BootClockRUN(void)
{
/*
* Core clock: 119.808MHz
* Bus clock: 59.904MHz
*/
const mcg_pll_config_t pll0Config = {
.enableMode = 0U,
.prdiv = 0x03U, // divide by 4
.vdiv = 0x0fU, // multiply by 39
};
const sim_clock_config_t simConfig = {
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.er32ksrc=2U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(4),
};
CLOCK_SetSimSafeDivs();
BOARD_InitOsc0();
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
CLOCK_SetSimConfig(&simConfig);
SystemCoreClock = 119808000U; // 12288000/4 * 39
}
void BOARD_InitOsc0(void)
{
const osc_config_t oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
.capLoad = 0,
.workMode = kOSC_ModeOscHighGain,
.oscerConfig = {
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}};
CLOCK_InitOsc0(&oscConfig);
/* Passing the XTAL0 frequency to clock driver. */
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
}
firmware hangs in CLOCK_BootToPeeMode().
I want to make this clock path:

where am I wrong?
best regards
Max