HELP!!! Last bit of Kinetis DSPI Byte Transfer is Trucated

[myke_predko]

Still struggling with trying to get SD Cards working with the K22F and I'm wondering about the dspi clock. 

As I mentioned in my previous post, the last bit of a byte transfer is truncated as you can see in this quick and dirty screenshot:

The bottom line is the dspi sck and you can see that the "low" half of the cycle is truncated into the first bit of the next transfer. 

The dspi was selected from PE with a clock speed of 375kHz with Clock cfg.4 on a FRDM-k22F board. 

I'm looking around and can't find any reason of what I'm doing wrong, 375kHz is a "Possible setting" so I presume that means that the clock is divided evenly (although evidence suggests this is not the case). 

Can anybody help?

Thanx,

myke

[myke_predko · Accepted solution]

So, I have gotten SD Cards working with the K22F with SPI.  I put the code on this https://community.freescale.com/message/612390 thread.

myke

[Kan_Li]

Hi Myke,

I found you posted similar thread in HELP!!! Last bit of Kinetis DSPI Byte Transfer is Trucated , do are they the same issue? is it fixed?

Have a great day,
Kan

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[myke_predko]

Hi Kan,

Yes, it is the same issue and it's fixed with declaring the variable:

uint32_t spi0_ctar0_reg;

and then, after the "DSPI_DRV_MasterConfigureBus" statement, put in:

  spi0_ctar0_reg = SPI0_CTAR0 & 0xFF3F0FFF;  //  Fill out last bit of each byte xfer

  spi0_ctar0_reg = spi0_ctar0_reg | 0x00C01000;

  SPI0_CTAR0 = spi0_ctar0_reg;

I can obviously simplify the three statements into one without a variable, but this allowed me to observe the progress of the operations. 

The values for the changed CTAR0 bits (the PCSSK and CSSK fields in particular) were determined by trial and error (get the GDB plugin that allows you to modify system registers as it will make actions like this a *lot* easier).  The K22F's RM was used for information on the CTAR0 register. 

Regards,

myke