Direct FRDM-KL43Z4 FlexIO register configuration

[shauldorf]

I’m trying to write program that generates PWM output on PTD2 (J2-4) and RED LED is continually blinking .

My problem is with FlexIO register access. On the first “FLEXIO->…” instruction the program corrupts probably with unsupported NMI.  

Sample program

// ==========   RED LED Configuration

   SIM->SCGC5 |= 0x2000;                   // enable clock to Port E

   PORTE->PCR[31] = 0x100;               // make PTE31 pin as GPIO for RED LED

   PTE->PDDR |= 0x80000000;            // make PTE31, output pin

   PTE->PDOR |= 0x80000000;          // turn off LED

// ========== FlexIO Configuration

   FLEXIO->CTRL |= 0x0;                    // FlexIO disable       

   SIM->SCGC5 |= 0x80000000;         // enable FLEXIO clock

   PORTD-> PCR[2] = 0x600;              // make PTD2 FXIO0 D2 (Alt. #6)

// PTD->PDDR |=0x4 ;                 // ???

   FLEXIO->TIMCTL[0] |= 0x430202;  

              // Timer CTL: TRGSEL=0, TRIGPOL=0, TRGSRC=1,PINCGG=3, PINSEL=2, PINPOL=0, TIMOD=2

   FLEXIO->TIMCFG[0] |= 0x0;             // Timer 0 Config.

   FLEXIO->TIMCMP[0] |= 0x58;

   FLEXIO->CTRL |= 0x1;

[shauldorf]

Hello Rong

The problem with FlexIO clock = MCGIRCLK was solved there is MCG_C1 register with IRCLKEN field which enables IRC8M module.

Thanks for your helpful and fast response support.

Hope to hear from you with my next questions.

BR

Shaul

[xiangjun_rong]

Hi, Shaul,

I suppose you have to enable the FlexIO gated clock before you access any FlexIO register. For your case, pls put the line

   SIM->SCGC5 |= 0x80000000;       as first line.

In other words, use the code like:

// ========== FlexIO Configuration

   SIM->SCGC5 |= 0x80000000;         // enable FLEXIO clock

   FLEXIO->CTRL |= 0x0;                    // FlexIO disable       

   PORTD-> PCR[2] = 0x600;              // make PTD2 FXIO0 D2 (Alt. #6)

// PTD->PDDR |=0x4 ;                 // ???

   FLEXIO->TIMCTL[0] |= 0x430202;  

              // Timer CTL: TRGSEL=0, TRIGPOL=0, TRGSRC=1,PINCGG=3, PINSEL=2, PINPOL=0, TIMOD=2

   FLEXIO->TIMCFG[0] |= 0x0;             // Timer 0 Config.

   FLEXIO->TIMCMP[0] |= 0x58;

   FLEXIO->CTRL |= 0x1;

Hope it can help you

BR

XiangJun Rong

[shauldorf]

Hello Rong

I forgot to inform you that I’m using FRDM-KL43Z4 board with KDS v3.2 and KSDK v2.

I think that the problem is that with the “Build” process which generates hard fault during run time.

Unfortunately I’m not skilled enough to handle this kind of problems.

BR

Shaul

[xiangjun_rong]

Hi, Shaul,

I am sorry. I think you have to select the FlexIO clock source with FLEXIOSRC bits in SIM_SOPT2, the default is 2b'00, which disable any clock.

BR

Xiangjun Rong

FlexIO Module Clock Source Select
Selects the clock source for the FlexIO transmit and receive clock.
00 Clock disabled
01 IRC48M clock
10 OSCERCLK clock
11 MCGIRCLK clock

[shauldorf · Accepted solution]

Thanks

It is working but only with FlexIO clock = MCGPCLK ( b01).

I tried also options with FlexIO clock = MCGIRCLK (which by default is 8MHz and can be divided), but there is no output on selected Timer output (PTD2).

Is it somehow connected to gated clock, if yes how to enable this clock ?

Regards

Shaul

[shauldorf]

Hello Rong

I put the FlexIO clock enable before any access to FlexIO port it doesn’t solve the problem.

The firs access to FlexIO register generates the problem.

In attached file you can see my source file.

Regards

Shaul

[xiangjun_rong]

Hi,

I suppose that you do not enable PORTD gated clock because of using    PORTD-> PCR[2] = 0x600;, pls use the code:

SIM->SCGC5 |= 0x3000;  //enable PORTE and PORTD

Hope it can help you

BR

XiangJun Rong

[shauldorf]

Hi;

Doesn’t solve the problem. Ports D, E and FlexIO are clocked still Hard Fault interrupt

Shaul