scanning all ADC channels within DMA

cancel
Showing results for 
Search instead for 
Did you mean: 

scanning all ADC channels within DMA

Jump to solution
1,327 Views
arnoldbischof
Contributor III

I have designed a software driver which scans all AD channels of a MK10DN within DMA.

This device has some A channels and some B channels (e.g. ADC0.SE4a and ADC0.SE4b).

In my approach I use the PDB which cyclically triggers both AD channels A at 0 and B at half cycle time using the hardware trigger mode. Additionally I use one linked DMA channel which programs the channel selection into SC1A and SC1B alternately. For the transfer of the converted AD values, I use a second DMA channel which copies the RA and RB registers alternately into a table in RAM. The second DMA is triggered by ADC conversion complete.

This approach works fine for AD channels without suffix A and B (e.g. ADC0.SE8 and ADC0.SE9) but the A/B channel pairs (e.g. ADC0.SE4a and ADC0.SE4b) do not work proper. I see the same converted value in the values table for the A and B channel whereas the voltages on a and b are different.

I need some help to get the A and B channels within DMA

Labels (1)
Tags (3)
0 Kudos
1 Solution
110 Views
mjbcswitzerland
Specialist V

Arnold

My understanding is that the HW hardware trigger mode is controlling the A and B channels of the ADC. It is not controlling the A/B MUX of the input pins connected to the A/B channels, which is controlled by ADC0_CFG2.

Therefore, if you consider the two ADC inputs ADC0_SE5a and ADC0_SE5b you can connect them to an ADC channel by selecting ADC6a or AD6b in SC1n[ADCH] but the physical pin is still connected to either the a or b pin, depending on the ADCx_CFG2[MUXSEL] bit.

If you look at the table 3.7.1.3.1 ADC0 Channel Assignment for 144-Pin Package (for example) there is a foot-note (number 5) for such inputs which states: "ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter for details".

Therefore I believe that two settings need to be changed (channel and MUX) each time these are switched between.

Regards

Mark

View solution in original post

0 Kudos
8 Replies
110 Views
mjbcswitzerland
Specialist V

Hi

The A/B mux setting is controlled in ADCx_CFG2.

Is this being updated according as the DMA sequencing progresses? Maybe you can add a DMA write to it configure the input selection, synchronised to one of your DMA triggers?

Regards

Mark

110 Views
arnoldbischof
Contributor III

Hi Mark, thanks for your support.

I understand the reference manual documentation in that way, that if I use the PDB as hardware trigger on channel A and channel B, the control of the Mux is done by the trigger mechanism.

I think your suggestion, with a third DMA channel which controls the Mux in the ADC0_CFG2 would work. But I have only 4 DMA channels available on the MK10. 2 DMA channels are used by a SPI interface and 2 channels are used by the ADC-DMA mechanism. So there is no DMA channel left and my goal is to realize the ADC-DMA mechanism with 2 DMA channels.

I hope someone has as good solution for my problem :smileysad:

0 Kudos
111 Views
mjbcswitzerland
Specialist V

Arnold

My understanding is that the HW hardware trigger mode is controlling the A and B channels of the ADC. It is not controlling the A/B MUX of the input pins connected to the A/B channels, which is controlled by ADC0_CFG2.

Therefore, if you consider the two ADC inputs ADC0_SE5a and ADC0_SE5b you can connect them to an ADC channel by selecting ADC6a or AD6b in SC1n[ADCH] but the physical pin is still connected to either the a or b pin, depending on the ADCx_CFG2[MUXSEL] bit.

If you look at the table 3.7.1.3.1 ADC0 Channel Assignment for 144-Pin Package (for example) there is a foot-note (number 5) for such inputs which states: "ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter for details".

Therefore I believe that two settings need to be changed (channel and MUX) each time these are switched between.

Regards

Mark

View solution in original post

0 Kudos
110 Views
arnoldbischof
Contributor III

Hi Mark, Ok

My observations confirm your statements. If I set Mux in CFG2 to A(default) and run my ADC-DMA mechanism, I see that all A channels are correct and the B channels are incorrect. If I set the Mux to B and run the ADC-DMA mechanism, I see that all A channels are correct and the A channels are incorrect.

My next question is: If I set Mux to B, do I have to control the ADC with the SC1A and get the converted value out of RA ?

0 Kudos
110 Views
mjbcswitzerland
Specialist V

Arnold

As noted, the ADC chanel (SC1A or SC1B) is not related to the pin MUX setting so it is possible to read on ADC channel A or B, whether the MUX is set to A or B.

Retards

Mark

0 Kudos
110 Views
arnoldbischof
Contributor III

Mark

I have now a satisfying solution for the ADC read of all AD channels within 2 DMA channels.

In my new approach I use the PDB which cyclically initiates the channel selection DMA within an interrupt routine. This DMA programs the channel selection from channel selection RAM table, which is splitted into A channels and B channels sequentially into SC1A. For the transfer of the converted AD values, I use a second DMA channel which copies the RA register into an AD values table in RAM. The channel selection DMA is linked to the second DMA and will be started after the transfer of the converted value is done. I program the DMAs initial for the number of A channels to transfer and use a DMA transfer completed interrupt. This interrupt fires after all A channels are converted. In the interrupt handler I change the MUX to channel B and modify the DMA settings to copy as next action number of B channels to transfer and restart the channel selection DMA. The B channels will be converted and transferred into the values table then. In the next DMA transfer completed interrupt (after the B channels are converted) I change the MUX back to channel A and modify the DMA settings to copy as next action number of A channel DMA transfers.

This approach works fine for all AD channels now.

0 Kudos
110 Views
mjbcswitzerland
Specialist V

Arnold

That is good news.

Thanks for the feedback.

Regards

Mark

0 Kudos
110 Views
mjbcswitzerland
Specialist V

Hi All

I have found that the input selection at the ADCs is often a source of misunderstanding and have recently added an illustration and short discussion in Appendix D of the following document that may help:
http://www.utasker.com/docs/uTasker/uTaskerADC.pdf

Regards

Mark

0 Kudos