reset

[wuyewu]

Hello,

    I am developing MK21. I connect the reset pin with 10k res and 1uf cap,and EZP_CS to ground. But after reset ,i only get 1.5V reset signal level. I observed the waveform, and found periodic oscillation. Then i remote the cap, and found the reset pin was kept low and suddenly flush to high shortly and then back to low,periodically.  Only connecting EZP_CS to high, the reset signal can be normal.  I don't know why.

[wuyewu]

Hello Rastislav,

  At the beginning, I left the EZP_CS unconnected which was measured high level,1.  I just want to run the chip, and load booter into MCU. I plan to use Jlink to download。 But Jlink showed orange light which means the chip was in reset state.

And I test the reset pin. The result shows 1.5V. The waveform shows periodic oscillation. 

  After that, I think the chip can't leave the reset mode.So I connect the EZP_CS to high. And it works.  But as you said, I don't want to enter EZP mode.  

 Thanks for your help.

Regards, Wuye

[rastislav_pavlanin]

Hello Wuye,

if you do not want to utilize EZ_PORT then my suggestions are:

- keep EZP_CS high during reset (NOTE: do not forgot to take time constants (if RC components connected on RESET and PTA4) into account, the time constant on PTA4 must be much lower than on reset, if this conditions are not meet it could happend that during reset the low level is detected on PTA4 which at the end will results in EZ_PORT mode)

- disable EZ_PORT as mentioned before by EZPORT_DIS bit field in FOPT must be 0 in flash configuration field (flash location 0x40C). This part of flash is affecting the contant of FTFx_FOPT register content after reset. The values from flash configuration field (inlcuding FOPT, FSEC etc.) are copied into the FTFx_FOPT, FTFx_FSEC etc registers during reset condition (before reset is released) which at the end configure the device at reset..

regards

R.

[rastislav_pavlanin]

Hello Wuye,

Why EXP_CS is grounded? If you want to enter ez_port mode (serial flash programming) you need to assert the EZ_PORT CS for at least for 2 bus clocks after reset deassertion (not required to keep it at low level, well must not be keep low as it will caused system reset).

NOTE: do not forget that EZP_CS signal is inverted. 0 - enabled.

If you do not want to use ez_port functionality you can easily disable it via flash configuration field, especially FOPT[EZPORT_DIS].

regards

R.