power consumption when executing out of SRAM

[biosbob]

i have a very-low power application which (conveniently) can fit entirely in SRAM....

in general, what's the cost of executing out of on-chip FLASH versus on-chip SRAM???  feel free to reference any specific kinetis device (cortex M0+ preferred) as an example....

i assume i'm already powering the SRAM; and i know that FLASH is often put into "doze" mode when in VLLSx...  it just wasn't obvious from any of the data sheets how much power (uA/mHz) the FLASH itself consumes when the processor is active....

[biosbob]

i'm using several different boards, including the FRDM-KW38....

as i was looking through the datasheets of some LPC (cortex-m0+) parts, they all had a coremark score for SRAM and FLASH at different clock speeds....  on the LPC51U68, for instance, they quoted 62uA/MHz (SRAM) and 78uA/MHz (FLASH) with a 48 MHz clock....  the ratio between SRAM and FLASH was roughly the same at other clock speeds....

at this time, i'm looking for high-level confirmation that i would see similar improvement on comparable kintetis MCUs....

[CarlosGarabito]

Hi @biosbob  I'd highly recommend you to refer to the application note which illustrates the system performance running on the different memory devices (https://www.nxp.com.cn/docs/en/application-note/AN12437.pdf).

[CarlosGarabito]

Which evaluation board are you using?