i am new to the Kinetis K60_120 MHz family. we are looking at this part to implement a memory controller interface to NAND flash with ECC.
From reading the K60 Sub-Family reference manual with addendum, i think i understand how the ECC is being used to correct the data and how the main data is organized in conjunction with the ECC.
however, i do not see any mention about the possibility of ECC bit itself got flipped and how to protect and correct the flipped ECC bit in the spared area? The flipped possibility is small as the spared area is a lot smaller than the main data area, but it can happen.
Atmel SAM3x Nand flash controller has the parity associated with the ECC in the spare area where application can do the correction.
I wonder if Kinetis K60 has something like that.
I did a little experiment hope that will clear your doubt.
First, save and read back a page with ECC set to 32-bytes ECC. Save off the 60 ECC bytes (HW generated) at the end of the spare bytes. Save a page without HW ECC bytes enabled, but with previous save ECC bytes and has random one bit flipped in ECC bytes, then read back with HW ECC enabled. The content of the page data is unchanged, but the algorithm has change in the 60-ECC bytes.
Attached is the sample code, user can change any bit in the eccbytes array.
The ECC protects and corrects both data and ECC bytes.
As long as the error number in one page (subpage) is less than or equal to the correction ability (defined by ECC_MODE), all the errors in that page can be corrected, no matter the error location is in data or ECC.
Thanks for the clarification.
Unfortunately I am unable to see your contact email (strange thing). Can you please send me a message to:
I have also notified my colleagues in Austin/TX, so I hope somebody will contact you with the NDA and maybe they can assist you directly.
If I understood it properly, you just want to know, how the flash controller handles with the ECC errors.
This is one of the good questions, I cannot answer directly. Nobody cares about the NAND flash controller, it is just working somehow. I am very surprised, it is not documented well.
Seriously, I will look to the design PDM and contact the appropriate design people to answer this.
This can take some time, so please be patient.
Thank you. Please let us know as soon as you find out the info. this is very critical for us to evaluate how the ECC bits themselves are detected (flipped). as long as we know the ECC bits are no longer valid, that is ok, but we would like to know.
I have found the NFC block guide, with more information included. I don't know, if this will really answer everything to you.
But we cannot share this document with everybody.
What is your company / project please?
Maybe we can share this under the signed NDA (Non disclosure agreement)
Thank you for looking into this.
I work for Schlumberger in Houston Texas and we are looking at the feasibility of the 16GB memory for downhole application. this is to collect measurement data so we need to ensure our NAND flash is ECC protected and the ECC bits error themselves can be detected as well (not expect to be corrected for ECC bits flipped).
I am very happy to sign any NDA. the email address that i signed up for the forum is my work email. please send NDA directly to it. if you need my work email again, please let me know your work email and i can send it directly to you.