Hi,
I have found register addresses in the document you provided. Many thanks!
Now I'm trying to execute my first assembler code with this board based on a version I have for another board and I got some errors:
1. There are some compilation errors. However, the .axf is generated. I guess the error is in the .c files, which it is supposed that I'm not using. I guess for this reason they are not critical. Am I ok? how can I remove this .c and .h files from the target?
Rebuild started: Project: FRDMexample
*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
Rebuild target 'Target 1'
assembling FRDMexample.s...
assembling startup_MK64F12.s...
compiling system_MK64F12.c...
compiling startup.c...
C:\Users\faundez\AppData\Local\Arm\Packs\Keil\Kinetis_SDK_DFP\2.3.0\platform\devices\startup.c(68): warning: #47-D: incompatible redefinition of macro "__VECTOR_TABLE" (declared at line 126 of "C:\Users\faundez\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h")
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
C:\Users\faundez\AppData\Local\Arm\Packs\Keil\Kinetis_SDK_DFP\2.3.0\platform\devices\startup.c: 1 warning, 0 errors
linking...
.\Objects\FRDMexample.axf: Warning: L6914W: option ro-base ignored when using --scatter.
.\Objects\FRDMexample.axf: Warning: L6914W: option rw-base ignored when using --scatter.
.\Objects\FRDMexample.axf: Warning: L6340W: options first and last are ignored for link type of scattered
./RTE/Device/MK64FN1M0VLL12/MK64FN1M0xxx12_flash.scf(90): warning: L6314W: No section matches pattern *(InRoot$$Sections).
Program Size: Code=380 RO-data=1040 RW-data=0 ZI-data=2048
Finished: 0 information, 4 warning and 0 error messages.
".\Objects\FRDMexample.axf" - 0 Error(s), 5 Warning(s).
Build Time Elapsed: 00:00:06
Load "C:\\Keil\\ejemplo\\Objects\\FRDMexample.axf"
Internal DLL Error
Error: Flash Download failed - Target DLL has been cancelled
Flash Load finished at 00:14:40
2. When I try to load the code in the FRDMK64 board I got the following error: no ulink2/ME device. I think this is because I have not setup the proper debug. According to Keil it seems that this board uses JTAG/SW (MDK5 - NXP FRDM-K64F ). However, I do not see this option available in keil 5.29. How should I fix that? Please, consider that this is my first time trying to work with this development board. My previous experience is with launchpad TIVA TM4C123 mainly in C

This is my assembler code, based on a document "GPIO example in Kinetis design studio (KDS) with FRDM-K64F" by Paul Garate & Augusto Panecatl
thanks in advance
; Assembler example
; SW2 press -> green color
; SW3 press -> blue color
; SW2 and SW3 pressed -> red color
SIM_SCGC5 EQU 0x40048038 ;clock activation
PORTB_PCR21 EQU 0x4004A054;Blue led
PORTB_PCR22 EQU 0x4004A058;Red led
PORTE_PCR26 EQU 0x4004D068;Green led
PORTC_PCR6 EQU 0x4004B018; switch 2
PORTA_PCR4 EQU 0x40049010; swith 3
GPIOA_PDDR EQU 0x400FF014; Port A Data Direction Register
GPIOB_PDDR EQU 0x400FF054; Port B Data Direction Register
GPIOC_PDDR EQU 0x400FF094; Port C Data Direction Register
GPIOE_PDDR EQU 0x400FF114; Port E Data Direction Register
GPIOC_PDIR EQU 0x400FF090; Port C Data Input Register
GPIOA_PDIR EQU 0x400FF010; Port A Data Input Register
GPIOB_PDOR EQU 0x400FF040; Port B Data Output Register
GPIOE_PDOR EQU 0x400FF100; Port E Data Output Register
SEC_DIV_FIVE EQU 1066666 ; 1 second divided by 5
AREA |.text|,CODE,READONLY, ALIGN=2
THUMB
EXPORT __main
__main
BL GPIO_Init
Loop
LDR R0,=SEC_DIV_FIVE
BL delay
LDR R1,=GPIOC_PDIR
LDR R0,[R1]
CMP R0,#0x00 ;Switch 2 was pressed
BEQ SWITCH2_ON
LDR R1,=GPIOA_PDIR
LDR R0,[R1]
CMP R0,#0x00 ;Switch 3 was pressed
BEQ SWITCH3_ON
B Loop
SWITCH2_ON ;turn on green
MOV R0,#0x04000000
LDR R1,=GPIOE_PDOR
STR R0,[R1]
B Loop
SWITCH3_ON ;turn on blue
MOV R0,#0x00400000
LDR R1,=GPIOB_PDOR
STR R0,[R1]
B Loop
BOTH_SWITCHES ;turn on red
MOV R0,#0x00200000
LDR R1,=GPIOB_PDOR
STR R0,[R1]
B Loop
delay
SUBS R0,R0,#1
BNE delay
BX LR
GPIO_Init
LDR R1,=SIM_SCGC5
LDR R0,[R1]
ORR R0,R0,#0x2700 ;Port A, B, C, E
STR R0,[R1]
LDR R1,=PORTB_PCR21
MOV R0,#0x100
STR R0,[R1]
LDR R1,=PORTB_PCR22
MOV R0,#0x100
STR R0,[R1]
LDR R1,=PORTE_PCR26
MOV R0,#0x100
STR R0,[R1]
LDR R1,=PORTC_PCR6
MOV R0,#0x100
STR R0,[R1]
LDR R1,=PORTA_PCR4
MOV R0,#0x100
STR R0,[R1]
LDR R1,=GPIOA_PDDR
MOV R0,#0x0010
STR R0,[R1]
LDR R1,=GPIOB_PDDR
MOV R0,#0x00600000
STR R0,[R1]
LDR R1,=GPIOC_PDDR
MOV R0,#0x00000040
STR R0,[R1]
LDR R1,=GPIOE_PDDR
MOV R0,#0x04000000
STR R0,[R1]
BX LR
ALIGN
END