dma config issue

[gnichimohamed]

Hello

I want to scan 3 ADC channels with eDMA using two dma channels 0 an 1 on K02 microcontroller. So far my config should make it work but i don't find why it doesn't work.

SIM->SCGC6 |= SIM_SCGC6_ADC0_MASK; //enable clock for ADC0
ADC0->SC2 |=ADC_SC2_DMAEN_MASK;
ADC0->CFG1|=ADC_CFG1_MODE(0x03)|ADC_CFG1_ADIV(0x02)|ADC_CFG1_ADLSMP_MASK;
ADC0->CFG2|=ADC_CFG2_ADHSC_MASK|ADC_CFG2_ADLSTS(0);
ADC0->SC3 |=ADC_SC3_CAL_MASK;
while(ADC0->SC3 & ADC_SC3_CAL_MASK){};
ADC0->SC1[0] = ADC_SC1_ADCH(31);
ADC0->SC1[0]|=ADC_SC1_AIEN_MASK;
/* DMA */
SIM->SCGC6|= SIM_SCGC6_DMAMUX_MASK;
SIM->SCGC7|= SIM_SCGC7_DMA_MASK;
DMAMUX->CHCFG[FIRSTDMACHANNEL]&=~DMAMUX_CHCFG_ENBL_MASK;
DMAMUX->CHCFG[FIRSTDMACHANNEL]|=DMAMUX_CHCFG_SOURCE(63);//DMA source is an array
DMAMUX->CHCFG[FIRSTDMACHANNEL]|=DMAMUX_CHCFG_ENBL_MASK;
DMA0->TCD[FIRSTDMACHANNEL].SADDR=(uint32_t)&adc_mux[0];//source is adc_mux array for channel config
DMA0->TCD[FIRSTDMACHANNEL].DADDR=(uint32_t)&(ADC0->SC1[0]);
DMA0->TCD[FIRSTDMACHANNEL].SOFF=0x01;
DMA0->TCD[FIRSTDMACHANNEL].DOFF=0;
DMA0->TCD[FIRSTDMACHANNEL].ATTR=DMA_ATTR_SSIZE(0)| DMA_ATTR_DSIZE(0);
DMA0->TCD[FIRSTDMACHANNEL].NBYTES_MLNO=0x01;
DMA0->TCD[FIRSTDMACHANNEL].CITER_ELINKNO=0x03;
DMA0->TCD[FIRSTDMACHANNEL].BITER_ELINKNO=0x03;
DMA0->TCD[FIRSTDMACHANNEL].SLAST=-3;
DMA0->TCD[FIRSTDMACHANNEL].CSR=0;
DMA0->TCD[FIRSTDMACHANNEL].DLAST_SGA = 0x00;
DMAMUX->CHCFG[SECONDDMACHANNEL]&=~DMAMUX_CHCFG_ENBL_MASK;
DMAMUX->CHCFG[SECONDDMACHANNEL]|=DMAMUX_CHCFG_SOURCE(40);//DMA source is an ADC0
DMAMUX->CHCFG[SECONDDMACHANNEL]|=DMAMUX_CHCFG_ENBL_MASK;
DMA0->TCD[SECONDDMACHANNEL].SADDR=(uint32_t)&(ADC0->R[0]);
DMA0->TCD[SECONDDMACHANNEL].DADDR=(uint32_t)&adc_result[0];
DMA0->TCD[SECONDDMACHANNEL].SOFF=0;
DMA0->TCD[SECONDDMACHANNEL].SLAST=0x00;
DMA0->TCD[SECONDDMACHANNEL].DOFF=0x02;
DMA0->TCD[SECONDDMACHANNEL].ATTR=DMA_ATTR_SSIZE(1)|DMA_ATTR_DSIZE(1);
DMA0->TCD[SECONDDMACHANNEL].NBYTES_MLNO=0x02;
DMA0->TCD[SECONDDMACHANNEL].CITER_ELINKYES= DMA_CITER_ELINKYES_ELINK_MASK|
DMA_CITER_ELINKYES_LINKCH(FIRSTDMACHANNEL)|
DMA_CITER_ELINKYES_CITER(0x0C);
DMA0->TCD[SECONDDMACHANNEL].BITER_ELINKYES=DMA_BITER_ELINKYES_ELINK_MASK|
DMA_BITER_ELINKYES_LINKCH(FIRSTDMACHANNEL)|
DMA_BITER_ELINKYES_BITER(0x0C);
DMA0->TCD[SECONDDMACHANNEL].DLAST_SGA = -24;
DMA0>TCD[SECONDDMACHANNEL].CSR=DMA_CSR_MAJORELINK_MASK

                                                         |DMA_CSR_MAJORLINKCH(FIRSTDMACHANNEL);
ADC0->SC1[0]=ADC_SC1_ADCH(0x14); // trigger first conversion

I am using the exact same dma config from this post:https://community.nxp.com/message/837236 

[Hui_Ma]

Hi

I do a demo software for your reference.

Please refer attached example code for the detailed info.

The demo was tested with TWR-K60D100M board.

The default IAR project could be downloaded from here.

Wish it helps.

best regards,

Hui

[gnichimohamed]

Hi Hui,

Thank you for your answer, i don't understand why we need that ADC0_SC1A [AIEN] bit set. I have found that for my config that i didn't set the DMA_ERQ.

[Hui_Ma · Accepted solution]

Hi

You are right.

There doesn't need to set the ADC0_SC1A [AIEN] bit, the DMA was triggered by ADC0_SC1A[COCO] bit.

There are some modules need to enable both the interrupt and DMA bits, while the ADC module is an exception.

Sorry for  my previous answer. Customer just using below ADC channel scan line:

volatile unsigned char  uc_adc_mux[6]     = {17, 18, 16 };                //Mux scan line

Thank you for the attention.

Have a great day,
Ma Hui
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[joshuawillis]

Hi Ma Hui,

I'm attempting to port the code example you've provided to the FRDM-KV31F platform using MCUXpresso. At a customer's request, I'm writing register level code, and trying to minimize abstraction, so I'm not using the KSDK.

My questions are around the DMAMUX configuration for this part. 

I've been looking through the dma_request_source_t table to find appropriate values for both the DMA and ADC0 source. 

I've found the correct value for the ADC0 to be 0x40 for the DMAMUX->CHCFG[1]. I'm having trouble locating the correct value to enter into the DMAMUX->CHCFG[0] for the DMA Source. 

Any help in this porting effort would be greatly appreciated.

  //****************************************************************************
 //**** DMA channel 0, use for Write ADC mux channel, form SRAM to ADC ********
 //****************************************************************************
 DMAMUX->CHCFG[0] = DMAMUX_CHCFG_ENBL_MASK|DMAMUX_CHCFG_SOURCE(0x36); //DMA source DMA Mux

  //****************************************************************************
 //**** DMA channel 1, use for Read ADC result data, form ADC to SRAM *********
 //****************************************************************************
 //NVIC_SetIsr(INT_DMA1,2); //17

 DMAMUX->CHCFG[1] = DMAMUX_CHCFG_ENBL_MASK|DMAMUX_CHCFG_SOURCE(kDmaRequestMux0ADC0); //DMA source ADC0

Bets regards,

Josh

[Hui_Ma]

Hi Josh,

Sorry for the later reply.

The KV31 DMA request source number in decimal.

If you want to select ADC0 as DMA channel0 trigger source, the register of DMAMUX_CHCFG0 [SOURCE] bits should be 0x28.

Wish it helps.

Have a great day,
Ma Hui

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