about the address phase of FLEXBUS

[okubohitoshi]

I have a question about the address phase of FLEXBUS.

(using MK20FN1M0VLQ12 of KInetis K series MCUs)

When I observed FLEXBUS with an oscilloscope, 2 cycles (bus clock) may be taken [ after an address bus and write enable changing ] for chip select to change.

By the catalog, it is 1cycle.

Please let me know the conditions used as 2cycle.

[Hui_Ma]

Please check the FlexBus Chip select control register (FB_CSCRn) [ASET] bits setting, which will affect FB_CS signal assert time.

Wish it helps.

Best regards,

Ma Hui

[okubohitoshi]

I confirmed that it became ”(FB_CSCRn) [ASET] bits setting is 00b" .

Having become clear after that is shown below.

1.The 1st write is 1 clock, the 2nd write and after is 2 clocks .

2.After memory read (bus access) , it returns to 1 clock. And the 2nd write and after is 2 clocks .

3.When (FB_CSCRn) [ASET] bits setting is 01b, the 1st write is 2 clock, the 2nd write and after is 3 clocks .