Why is my application intermittently failing to start properly when being loaded by a bootloader?

aaronledger · ‎01-15-2015

I am using the K22FN1M0 part and having an issue where a small number of processors seem to be affected. The problem is that sometimes, the main application seems to fail to run properly intermittently. The same exact code will run on other parts seemingly just fine. When I say fails to run properly, I mean we get behavior as if it were some unhandled exception. If the code is slightly altered and recompiled, the processors that were failing may behave as expected. I'm looking for some ideas about how to troubleshoot this further.

I am using a custom bootloader that essentially does the following:

__disable_irq();

uint32_t new_sp = IMAGE_ADDR[0];

uint32_t new_pc = IMAGE_ADDR[1];

SCB->VTOR = (uint32_t)BLOCK1_BASE;

asm("mov LR, 0xFFFFFFFF");

__set_MSP(new_sp);

__set_PSP(new_sp);

((void(*)(void))new_pc)();

In this case, IMAGE_ADDR is the 2nd flash block (also BLOCK1_BASE) where the main application is located. Note that the processor startup code is shared in both main application and bootloader. Before utilizing a bootloader, this type of issue was not observed. I have altered the main application to not run some of the startup code that is already run by the bootloader, but it had no affect on the issue. Are there certain items in startup that if run a second time could result in some behavior like this? Any insight is appreciated.

Kan_Li · ‎02-05-2015

Hi Aaron Ledger,

Would you please tell us which boot loader you are using , and the version info? is it a custom boot loader? Please kindly help to clarify.

Thanks for your patience!

Kan

mjbcswitzerland · ‎02-05-2015

Aaron

When your boot loader completes its work (also when not actually loading anything) have you verified that all peripherals and interrupts that it enabled are disabled?

I work a lot with boot loaders and have occasionally had effects where occasionally a spurious interrupt is received at the application. Even with the same software it can seem fine for some time and then suddenly do it.

Recently I had this case:

- the boot loader uses SYSTICK

- the application uses the low power timer for its TICK and doesn't enabe the SYSTICK or its interrupts in the NVIC

- occasionally I has a case where there was a spurious interrupt

- I found that writes to the NVIC used to disable all previously used interrupts by the loader were operating normally for the peripherals but I could see that the SYSTICK flags were "sticking". Not understanding why, I disabled the SYSTICK instead and this solved the issue.

It may be worth setting a break point at the jump from loader to application and checking through all interrupt registers to see whether something is pending/enabled. This is how I saw that there was something in thixs case that obviously could sometimes cause problems. It is also when I found that the SYSTICK masks in the NVIC (which I thought had been cleared) were sticking because I couldn't set them back with the debugger either (???).

Regards

Mark

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Kan_Li · ‎01-16-2015

Hi Aaron Ledger,

What did you do in your startup()? would you please share it for a review? and what do you mean the shared startup()? do boot loader and application call this startup() via a unique entry? Please kindly help to clarify. Thanks for your patience!

Have a great day,
Kan

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aaronledger · ‎01-16-2015

Here is the startup code being used. When I say shared, I mean that both the bootloader and then the main application run through the same startup routines below, however, I have defined __NO_SYSTEM_INIT for the main application.

/* ---------------------------------------------------------------------------------------*/

/* @file: startup_MK22F12.s */

/* @purpose: CMSIS Cortex-M4 Core Device Startup File */

/* MK22F12 */

/* @version: 1.7 */

/* @date: 2014-2-18 */

/* @build: b140606 */

/* ---------------------------------------------------------------------------------------*/

/* */

/* Redistribution and use in source and binary forms, with or without modification, */

/* are permitted provided that the following conditions are met: */

/* */

/* o Redistributions of source code must retain the above copyright notice, this list */

/* of conditions and the following disclaimer. */

/* */

/* o Redistributions in binary form must reproduce the above copyright notice, this */

/* list of conditions and the following disclaimer in the documentation and/or */

/* other materials provided with the distribution. */

/* */

/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */

/* contributors may be used to endorse or promote products derived from this */

/* software without specific prior written permission. */

/* */

/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */

/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */

/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */

/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */

/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */

/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */

/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */

/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */

/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */

/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */

/*****************************************************************************/

/* Version: GCC for ARM Embedded Processors */

/*****************************************************************************/

.syntax unified

.arch armv7-m

.section .isr_vector, "a"

.align 2

.globl __isr_vector

__isr_vector:

.long __StackTop /* Top of Stack */

.long Reset_Handler /* Reset Handler */

.long NMI_Handler /* NMI Handler*/

.long HardFault_Handler /* Hard Fault Handler*/

.long MemManage_Handler /* MPU Fault Handler*/

.long BusFault_Handler /* Bus Fault Handler*/

.long UsageFault_Handler /* Usage Fault Handler*/

.long 0 /* Reserved*/

.long SVC_Handler /* SVCall Handler*/

.long DebugMon_Handler /* Debug Monitor Handler*/

.long 0 /* Reserved*/

.long PendSV_Handler /* PendSV Handler*/

.long SysTick_Handler /* SysTick Handler*/

/* External Interrupts*/

.long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete*/

.long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete*/

.long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete*/

.long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete*/

.long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete*/

.long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete*/

.long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete*/

.long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete*/

.long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete*/

.long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete*/

.long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete*/

.long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete*/

.long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete*/

.long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete*/

.long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete*/

.long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete*/

.long DMA_Error_IRQHandler /* DMA Error Interrupt*/

.long MCM_IRQHandler /* Normal Interrupt*/

.long FTFE_IRQHandler /* FTFE Command complete interrupt*/

.long Read_Collision_IRQHandler /* Read Collision Interrupt*/

.long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/

.long LLW_IRQHandler /* Low Leakage Wakeup*/

.long Watchdog_IRQHandler /* WDOG Interrupt*/

.long Reserved39_IRQHandler /* Reserved Interrupt 39*/

.long I2C0_IRQHandler /* I2C0 interrupt*/

.long I2C1_IRQHandler /* I2C1 interrupt*/

.long SPI0_IRQHandler /* SPI0 Interrupt*/

.long SPI1_IRQHandler /* SPI1 Interrupt*/

.long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt*/

.long I2S0_Rx_IRQHandler /* I2S0 receive interrupt*/

.long Reserved46_IRQHandler /* Reserved interrupt 46*/

.long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/

.long UART0_ERR_IRQHandler /* UART0 Error interrupt*/

.long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/

.long UART1_ERR_IRQHandler /* UART1 Error interrupt*/

.long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt*/

.long UART2_ERR_IRQHandler /* UART2 Error interrupt*/

.long UART3_RX_TX_IRQHandler /* UART3 Receive/Transmit interrupt*/

.long UART3_ERR_IRQHandler /* UART3 Error interrupt*/

.long ADC0_IRQHandler /* ADC0 interrupt*/

.long CMP0_IRQHandler /* CMP0 interrupt*/

.long CMP1_IRQHandler /* CMP1 interrupt*/

.long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/

.long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/

.long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/

.long CMT_IRQHandler /* CMT interrupt*/

.long RTC_IRQHandler /* RTC interrupt*/

.long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/

.long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/

.long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/

.long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/

.long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/

.long PDB0_IRQHandler /* PDB0 Interrupt*/

.long USB0_IRQHandler /* USB0 interrupt*/

.long USBDCD_IRQHandler /* USBDCD Interrupt*/

.long Reserved71_IRQHandler /* Reserved interrupt 71*/

.long DAC0_IRQHandler /* DAC0 interrupt*/

.long MCG_IRQHandler /* MCG Interrupt*/

.long LPTimer_IRQHandler /* LPTimer interrupt*/

.long PORTA_IRQHandler /* Port A interrupt*/

.long PORTB_IRQHandler /* Port B interrupt*/

.long PORTC_IRQHandler /* Port C interrupt*/

.long PORTD_IRQHandler /* Port D interrupt*/

.long PORTE_IRQHandler /* Port E interrupt*/

.long SWI_IRQHandler /* Software interrupt*/

.long SPI2_IRQHandler /* SPI2 Interrupt*/

.long UART4_RX_TX_IRQHandler /* UART4 Receive/Transmit interrupt*/

.long UART4_ERR_IRQHandler /* UART4 Error interrupt*/

.long UART5_RX_TX_IRQHandler /* UART5 Receive/Transmit interrupt*/

.long UART5_ERR_IRQHandler /* UART5 Error interrupt*/

.long CMP2_IRQHandler /* CMP2 interrupt*/

.long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt*/

.long DAC1_IRQHandler /* DAC1 interrupt*/

.long ADC1_IRQHandler /* ADC1 interrupt*/

.long I2C2_IRQHandler /* I2C2 interrupt*/

.long CAN0_ORed_Message_buffer_IRQHandler /* CAN0 OR'd message buffers interrupt*/

.long CAN0_Bus_Off_IRQHandler /* CAN0 bus off interrupt*/

.long CAN0_Error_IRQHandler /* CAN0 error interrupt*/

.long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning interrupt*/

.long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning interrupt*/

.long CAN0_Wake_Up_IRQHandler /* CAN0 wake up interrupt*/

.long SDHC_IRQHandler /* SDHC interrupt*/

.long DefaultISR /* 98*/

.long DefaultISR /* 99*/

.long DefaultISR /* 100*/

.long DefaultISR /* 101*/

.long DefaultISR /* 102*/

.long DefaultISR /* 103*/

.long DefaultISR /* 104*/

.long DefaultISR /* 105*/

.long DefaultISR /* 106*/

.long DefaultISR /* 107*/

.long DefaultISR /* 108*/

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.long DefaultISR /* 246*/

.long DefaultISR /* 247*/

.long DefaultISR /* 248*/

.long DefaultISR /* 249*/

.long DefaultISR /* 250*/

.long DefaultISR /* 251*/

.long DefaultISR /* 252*/

.long DefaultISR /* 253*/

.long DefaultISR /* 254*/

.long 0xFFFFFFFF /* Reserved for user TRIM value*/

.size __isr_vector, . - __isr_vector

/* Flash Configuration */

.section .FlashConfig, "a"

.long 0xFFFFFFFF

.long 0x7EFBFFFE

.equ _NVIC_ICER0, 0xE000E180

.equ _NVIC_ICPR0, 0xE000E280

.text

.thumb

/* Reset Handler */

.thumb_func

.align 2

.globl Reset_Handler

.type Reset_Handler, %function

Reset_Handler:

cpsid i /* Mask interrupts */

ldr r0, =_NVIC_ICER0 /* Disable interrupts and clear pending flags */

ldr r1, =_NVIC_ICPR0

ldr r2, =0xFFFFFFFF

mov r3, #8

_irq_clear:

cbz r3, _irq_clear_end

str r2, [r0], #4 /* NVIC_ICERx - clear enable IRQ register */

str r2, [r1], #4 /* NVIC_ICPRx - clear pending IRQ register */

sub r3, r3, #1

b _irq_clear

_irq_clear_end:

#ifndef __NO_SYSTEM_INIT

bl SystemInit

#endif

cpsie i /* Unmask interrupts */

/* Loop to copy data from read only memory to RAM. The ranges

* of copy from/to are specified by following symbols evaluated in

* linker script.

* __etext: End of code section, i.e., begin of data sections to copy from.

* __data_start__/__data_end__: RAM address range that data should be

* copied to. Both must be aligned to 4 bytes boundary. */

ldr r1, =__etext

ldr r2, =__data_start__

ldr r3, =__data_end__

#if 1

/* Here are two copies of loop implemenations. First one favors code size

* and the second one favors performance. Default uses the first one.

* Change to "#if 0" to use the second one */

.LC0:

cmp r2, r3

ittt lt

ldrlt r0, [r1], #4

strlt r0, [r2], #4

blt .LC0

#else

subs r3, r2

ble .LC1

.LC0:

subs r3, #4

ldr r0, [r1, r3]

str r0, [r2, r3]

bgt .LC0

.LC1:

#endif

#ifdef __STARTUP_CLEAR_BSS

/* This part of work usually is done in C library startup code. Otherwise,

* define this macro to enable it in this startup.

*

* Loop to zero out BSS section, which uses following symbols

* in linker script:

* __bss_start__: start of BSS section. Must align to 4

* __bss_end__: end of BSS section. Must align to 4

*/

ldr r1, =__bss_start__

ldr r2, =__bss_end__

movs r0, 0

.LC2:

cmp r1, r2

itt lt

strlt r0, [r1], #4

blt .LC2

#endif /* __STARTUP_CLEAR_BSS */

#ifndef __START

#define __START _start

#endif

bl __START

.pool

.size Reset_Handler, . - Reset_Handler

.align 1

.thumb_func

.weak Default_Handler

.type Default_Handler, %function

Default_Handler:

b .

.size Default_Handler, . - Default_Handler

/* Macro to define default handlers. Default handler

* will be weak symbol and just dead loops. They can be

* overwritten by other handlers */

.macro def_irq_handler handler_name

.weak \handler_name

.set \handler_name, Default_Handler

.endm

/* Exception Handlers */

def_irq_handler NMI_Handler

def_irq_handler HardFault_Handler

def_irq_handler MemManage_Handler

def_irq_handler BusFault_Handler

def_irq_handler UsageFault_Handler

def_irq_handler SVC_Handler

def_irq_handler DebugMon_Handler

def_irq_handler PendSV_Handler

def_irq_handler SysTick_Handler

def_irq_handler DMA0_IRQHandler

def_irq_handler DMA1_IRQHandler

def_irq_handler DMA2_IRQHandler

def_irq_handler DMA3_IRQHandler

def_irq_handler DMA4_IRQHandler

def_irq_handler DMA5_IRQHandler

def_irq_handler DMA6_IRQHandler

def_irq_handler DMA7_IRQHandler

def_irq_handler DMA8_IRQHandler

def_irq_handler DMA9_IRQHandler

def_irq_handler DMA10_IRQHandler

def_irq_handler DMA11_IRQHandler

def_irq_handler DMA12_IRQHandler

def_irq_handler DMA13_IRQHandler

def_irq_handler DMA14_IRQHandler

def_irq_handler DMA15_IRQHandler

def_irq_handler DMA_Error_IRQHandler

def_irq_handler MCM_IRQHandler

def_irq_handler FTFE_IRQHandler

def_irq_handler Read_Collision_IRQHandler

def_irq_handler LVD_LVW_IRQHandler

def_irq_handler LLW_IRQHandler

def_irq_handler Watchdog_IRQHandler

def_irq_handler Reserved39_IRQHandler

def_irq_handler I2C0_IRQHandler

def_irq_handler I2C1_IRQHandler

def_irq_handler SPI0_IRQHandler

def_irq_handler SPI1_IRQHandler

def_irq_handler I2S0_Tx_IRQHandler

def_irq_handler I2S0_Rx_IRQHandler

def_irq_handler Reserved46_IRQHandler

def_irq_handler UART0_RX_TX_IRQHandler

def_irq_handler UART0_ERR_IRQHandler

def_irq_handler UART1_RX_TX_IRQHandler

def_irq_handler UART1_ERR_IRQHandler

def_irq_handler UART2_RX_TX_IRQHandler

def_irq_handler UART2_ERR_IRQHandler

def_irq_handler UART3_RX_TX_IRQHandler

def_irq_handler UART3_ERR_IRQHandler

def_irq_handler ADC0_IRQHandler

def_irq_handler CMP0_IRQHandler

def_irq_handler CMP1_IRQHandler

def_irq_handler FTM0_IRQHandler

def_irq_handler FTM1_IRQHandler

def_irq_handler FTM2_IRQHandler

def_irq_handler CMT_IRQHandler

def_irq_handler RTC_IRQHandler

def_irq_handler RTC_Seconds_IRQHandler

def_irq_handler PIT0_IRQHandler

def_irq_handler PIT1_IRQHandler

def_irq_handler PIT2_IRQHandler

def_irq_handler PIT3_IRQHandler

def_irq_handler PDB0_IRQHandler

def_irq_handler USB0_IRQHandler

def_irq_handler USBDCD_IRQHandler

def_irq_handler Reserved71_IRQHandler

def_irq_handler DAC0_IRQHandler

def_irq_handler MCG_IRQHandler

def_irq_handler LPTimer_IRQHandler

def_irq_handler PORTA_IRQHandler

def_irq_handler PORTB_IRQHandler

def_irq_handler PORTC_IRQHandler

def_irq_handler PORTD_IRQHandler

def_irq_handler PORTE_IRQHandler

def_irq_handler SWI_IRQHandler

def_irq_handler SPI2_IRQHandler

def_irq_handler UART4_RX_TX_IRQHandler

def_irq_handler UART4_ERR_IRQHandler

def_irq_handler UART5_RX_TX_IRQHandler

def_irq_handler UART5_ERR_IRQHandler

def_irq_handler CMP2_IRQHandler

def_irq_handler FTM3_IRQHandler

def_irq_handler DAC1_IRQHandler

def_irq_handler ADC1_IRQHandler

def_irq_handler I2C2_IRQHandler

def_irq_handler CAN0_ORed_Message_buffer_IRQHandler

def_irq_handler CAN0_Bus_Off_IRQHandler

def_irq_handler CAN0_Error_IRQHandler

def_irq_handler CAN0_Tx_Warning_IRQHandler

def_irq_handler CAN0_Rx_Warning_IRQHandler

def_irq_handler CAN0_Wake_Up_IRQHandler

def_irq_handler SDHC_IRQHandler

def_irq_handler DefaultISR

.end

/*

** ###################################################################

** Compilers: ARM Compiler

** Freescale C/C++ for Embedded ARM

** GNU C Compiler

** GNU C Compiler - CodeSourcery Sourcery G++

** IAR ANSI C/C++ Compiler for ARM

**

** Reference manual: K22P144M100SF5RM, Rev.2, Apr 2013

** Version: rev. 1.7, 2014-02-18

**

** Abstract:

** Provides a system configuration function and a global variable that

** contains the system frequency. It configures the device and initializes

** the oscillator (PLL) that is part of the microcontroller device.

**

** http: www.freescale.com

** mail: support@freescale.com

**

** Revisions:

** - rev. 1.0 (2012-06-06)

** Initial version.

** - rev. 1.1 (2012-11-12)

** Update according to reference manual rev.1, draft B

** - rev. 1.2 (2012-12-04)

** Update according to reference manual rev.1

** - rev. 1.3 (2013-03-11)

** System initialization updated to add 120MHz clock option.

** - rev. 1.4 (2013-04-05)

** Changed start of doxygen comment.

** - rev. 1.5 (2013-05-16)

** Update according to reference manual rev.2

** - rev. 1.6 (2013-10-29)

** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.

** The declaration of clock configurations has been moved to separate header file system_xxxx.h

** Startup file for gcc has been updated according to CMSIS 3.2.

** Access restriction of some registers fixed.

** - rev. 1.7 (2014-02-18)

** UART0 module - LON registers removed.

**

** ###################################################################

*/

/*!

* @file MK22F12

* @version 1.7

* @date 2014-02-18

* @brief Device specific configuration file for MK22F12 (implementation file)

*

* Provides a system configuration function and a global variable that contains

* the system frequency. It configures the device and initializes the oscillator

* (PLL) that is part of the microcontroller device.

*/

#include <stdint.h>

#include "processor.h"

#if REF_CLK_FREQ == 27000000

#define FRDIV 0x05

#define PRDIV0 0x08

#define VDIV0 0x10

#elif REF_CLK_FREQ == 8000000

#define FRDIV 0x03

#define PRDIV0 0x01

#define VDIV0 0x06

#else

#error Unsupported ref clock freq

#endif

/* ----------------------------------------------------------------------------

-- SystemInit()

---------------------------------------------------------------------------- */

void SystemInit (void) {

#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))

SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */

#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */

/* Disable the WDOG module */

/* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */

WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */

/* WDOG_UNLOCK: WDOGUNLOCK=0xD928 */

WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */

/* WDOG_STCTRLH:

* ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,??=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0

* */

WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |

WDOG_STCTRLH_WAITEN_MASK |

WDOG_STCTRLH_STOPEN_MASK |

WDOG_STCTRLH_ALLOWUPDATE_MASK |

WDOG_STCTRLH_CLKSRC_MASK |

0x0100U;

/* System clock initialization */

/* SIM_CLKDIV1:

* OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0

* */

SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x03) | SIM_CLKDIV1_OUTDIV4(0x03); /* Set the system prescalers to safe value */

/* SIM_SCGC5: PORTA=1 */

SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */

if ((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) {

/* PMC_REGSC:

* ACKISO=1 */

PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */

}

/* SIM_CLKDIV1:

* OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0

* */

SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x01) | SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */

/* SIM_SOPT2: PLLFLLSEL=1

* */

SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */

/* SIM_SOPT1:

* OSC32KSEL=3 */

SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */

/* Switch to FBE

* Mode */

/* MCG_C2:

* LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0

* */

MCG->C2 = (MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK);

/* OSC_CR:

* ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0

* */

OSC->CR = OSC_CR_ERCLKEN_MASK;

/* MCG_C7:

* OSCSEL=0 */

MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);

/* MCG_C1:

* CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0

* */

MCG->C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(FRDIV) | MCG_C1_IRCLKEN_MASK);

/* MCG_C4:

* DMX32=0,DRST_DRS=0

* */

MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));

/* MCG_C5:

* ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=8

* */

MCG->C5 = MCG_C5_PRDIV0(PRDIV0);

/* MCG_C6:

* LOLIE0=0,PLLS=0,CME0=0,VDIV0=0x10

* */

MCG->C6 = MCG_C6_VDIV0(VDIV0);

while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */

}

while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */

}

while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */

}

/* Switch to PBE Mode */

/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x10 */

MCG->C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(VDIV0));

while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */

}

while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */

}

/* Switch to PEE Mode */

/* MCG_C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */

MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(FRDIV) | MCG_C1_IRCLKEN_MASK);

while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */

}

Kan_Li · ‎01-19-2015

Hi Aaron Ledger,

Thanks for the information! I have passed the above to our expert team for a review, and will let you know if I have any feedback.

Thanks for your patience!

Kan

Why is my application intermittently failing to start properly when being loaded by a bootloader?

Why is my application intermittently failing to start properly when being loaded by a bootloader?

Kinetis K Series MCUs