Hi, Matt,
From theory, the output signal falling/rising time is dependent only on the parasitic capacitance and driving current of the output gate, the parasitic capacitance is related to the trace and device on the PCB, but we specify the driving current of the output pin in data sheet. The High drive strength is 20mA, the Low drive strength is 5mA for both sink/source current under the condition of 5V logic for KE06, pls refer to section 5.1.1 DC characteristics in data sheet of KE06.
In the data sheet of KE06, We specify the rising/falling time of the Kinetis chip output signals, while we assume the external capacitor is about 50pF, pls refer to section 5.2.1 Control timing in data sheet of KE06. I attach the KE06 data sheet here.
BR
XiangJun Rong