What is default BUS/FLASH clock of S9KEAZ128A and how to choose FCLKDIV?

[danfin]

Goodmorning.

My question is about BUS/FLASH clock value after Power On Reset of S9KEAZ128A.

The IRC (internal reference clock should be in range of 31.25 kHz to 39.0625 kHz).

It is not clear because the range is so high. Shouldn't the internal crystal have a standard value of 32.768 kHz?

According to Reference Manual the default state of the clock distribution is :

-FEI mode enabled

-IRC is selected

-FLL multiply by 1280 the IRC

-The OUTDIV2 bit of SIM_CLKDIV is zero.

-defualt BDIV = 1 that means clocks divided by 2.

So the main clock is 31.25 * 1280 = 40 MHz and 39.0625*1280 = 50 MHz

Since BDIV the core clock should be 40/2 MHz and 50 /2 Mhz so it is in the range [20 - 25] MHz.

According to SIM_CLKDIV where OUTDIV2 that is 0 after power on reset, then the Core clock is not divided by 2.

So deafutl BUS/FLASH clock should be in the range of [20 - 25] MHz.

Is it correct?

Based on this reasoning I should choose the value of FCLKDIV between 0x14 and 0x18.

Is it correct?

Thank you for the answers

best regards

[Omar_Anguiano · Accepted solution]

Hello

Hope you are well, I will gladly answer your questions.
The IRC is trimmed in the range of 31.25 kHz to 39.0625 kHz to allow us to achieve exotic bus frequencies.
This document  the importance of trimming the clock: https://community.nxp.com/t5/8-bit-Microcontrollers-Knowledge/Trimming-the-S08P-MCU/ta-p/1118853

The values you calculated are for the ICSOUTCLK, we need to be careful about overpassing the maximum clock values, you can find these values in chapter 5.4.1 of the reference manual.

I would suggest a value between 0x13 and 0x17 since the maximum flash clock frequency is 24Mhz.

Let me know if this is helpful, if you have more questions do not hesitate to ask me.
Best regards,
Omar

[danfin]

Spoiler

Hello Omar,

really thank you for the answer.

I want only add one thing to your explanation.

From reference manual the base clock frequency is 37.5 kHz

Multipling this by FLL multiplier *1280 we have the ICSFLLCLK= 48 MHz so the core and bus frequency should be about 24 MHz.

This should be roughly the default clock frequency and the default FCLKDIV value to use is therefore 0x17.

Am i correct?

Thank you in advance.

Best regards