Ok let me wrap this up. We have pin 26 which 3.2.2.2 of the reference manual says is not NMI after reset (WRONG). We have pin 26 of the 64 pin package attached to an N channel mosfet with a pull down on the gate. NMI is active so hence the jump off the rails after reset and a brief run of SWD communications. If you look at the pin tables, the default function of pin 26 on a LQFP64 part IS NMI. Documentation needs updates. Also, the K22 Schematic cell for the part implies the NMI assignment implies NMI as secondary to the primary default configuration. This needs to be observed in ALL labels applied to schematic cells when naming pins so you know from looking at the schematic what mux configurations exist in order of the pin table as in
(64 pin LQFP) pin 26 -- LLWU_P3 NMI_b/ EZP_CS_b PTA4/ LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b
This way you know!
Hi Chris,
Please modify the circuit according the Fig 1, then give a shot again.
If you have any further questions about it, please feel free to contact with me.
Have a great day,
Ping
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Ok let me wrap this up. We have pin 26 which 3.2.2.2 of the reference manual says is not NMI after reset (WRONG). We have pin 26 of the 64 pin package attached to an N channel mosfet with a pull down on the gate. NMI is active so hence the jump off the rails after reset and a brief run of SWD communications. If you look at the pin tables, the default function of pin 26 on a LQFP64 part IS NMI. Documentation needs updates. Also, the K22 Schematic cell for the part implies the NMI assignment implies NMI as secondary to the primary default configuration. This needs to be observed in ALL labels applied to schematic cells when naming pins so you know from looking at the schematic what mux configurations exist in order of the pin table as in
(64 pin LQFP) pin 26 -- LLWU_P3 NMI_b/ EZP_CS_b PTA4/ LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b
This way you know!
Hi Chris,
Thank you for your interest in NXP Semiconductor products and the opportunity to serve you.
I was wondering if you can tell what the kind of MCG mode you set and illustrate the debug interface, then it can help me to figure out the root cause of the issue.
Have a great day,
Ping
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Hi Chris,
I think you may misunderstand my question, Let me clarify it.
I'd like to know what the kind of MCG mode you set the MCU in.
And I've also attached the Kinetis Peripheral Module Quick Reference and the attachment introduces the hardware considerations when using the Kinetis MCUs , then you can refer to it for details.
Have a great day,
Ping
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Hi Ping, I'm also working on this project with Chris and have a bit of info to add...
Our scenario is that we are trying to flash the MCU over the SWD interface with a USB Multilink Universal pod. The flashing process gets to about 61%, then KDS says it can't find the device.
To your question, the MCG mode is set to PEE and we have an external 12MHz oscillator as the external clk source as shown in the schematic above.
However to Chris' point, aren't the oscillator hardware and settings irrelevant until AFTER the MCU has been flashed because isn't the MCU running on it's own internal clk or the SWD_CLK during the flash process? Of course if the MCG settings aren't correct then the MCU will crash immediately after coming out of reset, but we can't even get through the flash process.
Thanks!
Jake
No I'm clear but I don't think you understand my situation. External clock sources appear to be optional from the documentation and should not be needed to get a connection to the chip through the SWD. This is our problem. We cannot even get to a point where we have code loaded to the MCU. So I need to know a reason why the attached circuit would not work with a multilink attached that works fine with the K22FRDM board. Again the MCG cannot be set by us because we cannot connect to the part to load code.