What are the maximum allowed GPIO input rise and fall times for a MK10DN processor?

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

What are the maximum allowed GPIO input rise and fall times for a MK10DN processor?

947 次查看
MikeAndrews
Contributor I

The K10 data sheet shows the maximum output rise and fall times dependent on capacitive load. But I don't see the maximum allowed input rise and fall times beyond which the input buffer's output could oscillate. Thanks.

标签 (1)
标记 (1)
0 项奖励
回复
1 回复

863 次查看
xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Mike,

As you said that we do not define the rising/falling time specs for GPIO pins in data sheet exactly, we only define the minimum time for the GPIO pin interrupt pulse width in section 5.3.2 General switching specifications in data sheet of K10 although the GPIO pins support edge triggering interrupt and DMA.

BR

XiangJun Rong

0 项奖励
回复