What are the maximum allowed GPIO input rise and fall times for a MK10DN processor?

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What are the maximum allowed GPIO input rise and fall times for a MK10DN processor?

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MikeAndrews
Contributor I

The K10 data sheet shows the maximum output rise and fall times dependent on capacitive load. But I don't see the maximum allowed input rise and fall times beyond which the input buffer's output could oscillate. Thanks.

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Mike,

As you said that we do not define the rising/falling time specs for GPIO pins in data sheet exactly, we only define the minimum time for the GPIO pin interrupt pulse width in section 5.3.2 General switching specifications in data sheet of K10 although the GPIO pins support edge triggering interrupt and DMA.

BR

XiangJun Rong

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