When compared to the K65, the K66 is slightly larger, has no anti-tamper pins, but has the same performance as the K65 w/ the CAU, power consumption, etc. One major difference was also that the K66 only supports 16-bit SDRAM interface vs. the K65's 32-bit SDRAM interface. Are these statements accurate (especially the SDRAM interface part)?
your statements are not accurate, the SDRAM controller of both K66 and K65 supports 8/16/32 bits SDRAM.
I copy the part from UM of K66:
The synchronous DRAM controller module provides glueless integration of SDRAM.
The key features of the DRAM controller include the following:
• Support for two independent blocks of SDRAM
• Interface to standard SDRAM components
• Programmable SRAS, SCAS, and refresh timing
• Support for 8-, 16-, and 32-bit wide SDRAM blocks
Hope it can help you
Here are the reasons why i think K66 only supports 16 bit wide SDRAM blocks and its likely documentation error on NXP's account.
1. If you look at K66P144M180SF5V2.pdf, the hardware manual, look at Figure 15, it only shows data bits from 31-16.
2. If you go to section 5 of the same doc, the pinout section and multiplexing assignments, you can only find 16 bits for the SDRAM data lines.
3. Also see this thread.
I just wanted confirmation from someone from NXP. Looks like documentation still hasn't been updated.