Using a GPIO for triggering and halting the eDMA on the kinetis K70 platform.

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Using a GPIO for triggering and halting the eDMA on the kinetis K70 platform.

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ClausStovgaard
Contributor III

Hi folks.

I have a setup where a FPGA is connected to a K70 MCU over the FlexBus. After some work writing and reading registers of the FPGA works quite well. Now I though have a problem, which I do not know how to solve.

I would like to use the eDMA of the Kinites to empty a FIFO on the FPGA. I have a pin from the FPGA connected to a GPIO of the MCU, indicating when there is 16 byte or more in the FIFO.  (It fits with the burst size of the eDMA). The data generated on the FPGA, is larger than what can be buffered in the FIFO, so I need to empty the FIFO while it is generated. I know how much data is generated, though not how fast it is generated, so the FPGA need to be able to halt the eDMA to prevent it reading garbage from a empty buffer.

So how to I set the DMA up to starting transferring when a GPIO change level up, and halting when changing level to down?

I have looked into the registers of the channel, but have not seen something, which can help me solve this problem.

Any ideas for how to easy empty a FIFO where I do not know how much data is available, but only how much data there is in the end is more than welcome.

Thanks ahead

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ClausStovgaard
Contributor III

Here is a small update for others reading this forum.

As the DMA has no halt input from the GPIO, it is a question about triggering when we have data enough for a minor loop. Next we need to trigger again, if there is data for another minor run. So the as I wrote before, we have solved it by making the output from the FPGA to be a pulsing output. So when there is 512 bytes or more in the FIFO the GPIO is pulsing and triggering the DMA. We of cause need some stuffing for being sure that the transfer is a multiple of 512 byte, but that is not a big issue.


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dieterteuchert
Contributor IV

I guess you need to route the DMA request signal from the external FPGA device through the GPIO into the DMAMUX and then into the DMA channel you want to use. Kinetis uses special counters to generate repeated DMA cycles with a continuous request signal. The while thing involves several steps of configuration, but using a debugger to do it step by step success is (almost) guaranteed. Depending on the debug environment you could wire a switch to the DMA request line to track the request signal in the peripheral registers.

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ClausStovgaard
Contributor III

Thanks for your input.

I have routed the DMA request signal through the DMAMUX and into the correct DMA channel. I did not think about using the periodically for transferring the data, so thanks for the input. As I understand it, it is the requests which it bloks, and not the DMA itself.

After some inspection of the reference manual, has I decided to try the following. Instead of having one transfer – e.g. one major loop, I will create a bunch of minor loop of 512 bytes. (Hope it does not degenerate performance too much). Next I will change the code in the FPGA from giving me a level signal when more than 16 byte is in the FIFO, to make pulses when there is more than 512 bytes in the buffer. With minor loops of 512 bytes, will I be able to setup transfers of 8 MB (14 bits for major loops), and I am not risking to empty the FIFO.

So here we go with testing.


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dieterteuchert
Contributor IV

Yes, there is no start/stop, but you need to clarify the meaning of the DMA request signal. In the sense of what is the data unit ready for transfer. Once the DMA triggers, you cannot make a partial transfer. The next data unit is the next transfer, and it will happen after the delay timer if the request signal remained active.

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ClausStovgaard
Contributor III

Here is a small update for others reading this forum.

As the DMA has no halt input from the GPIO, it is a question about triggering when we have data enough for a minor loop. Next we need to trigger again, if there is data for another minor run. So the as I wrote before, we have solved it by making the output from the FPGA to be a pulsing output. So when there is 512 bytes or more in the FIFO the GPIO is pulsing and triggering the DMA. We of cause need some stuffing for being sure that the transfer is a multiple of 512 byte, but that is not a big issue.


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