In my project the OSC is working with a 24MHz crystal, therefore MCG_C2[EREFS]= 1, but the routine builded in MCUXpresso 11.10.0 [build 3148] with SDK v.2.11.0 m.v.3.9.0 fall in infinite loop /* Wait for lock. */ even if crystal otion OSC selected (MCG_C2[EREFS]= 1):
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_CONFIG_EnableUsbhs0PhyPllClock
* Description : This function enables the internal 480MHz USB PHY PLL clock.
* Param src : USB HS PHY PLL clock source.
* Param freq : The frequency specified by src.
*
*END**************************************************************************/
static void CLOCK_CONFIG_EnableUsbhs0PhyPllClock(uint32_t freq) {
[..]
USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_BYPASS_MASK; /* Clear bypass bit */
USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; /* Clear to 0U to run clocks */
/* Wait for lock. */
while (!(USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK))
{
}
The workaround suggested in 0N65N Mask-Errata #e9712 not run.. possible?
Suggestions?
