USB driver for MK66 MCU (USB-HS device mode)

[edwinkaus]

I am working with MK66FN2M0VLQ18 MCU in our customized board.for the USB device mode.(USB High speed mode).

I have downloaded SDK_2.0_MK66FN2M0xxx18 , and running USB_DEVICE_CDC_VCOM .

It was running upto APPTASK() without any problem , but It has stopped in APPTASK(), and device is not getting detected in PC. 

Can anyone help me in resolving the issue as soon as possible.

Thank you.

[mjbcswitzerland]

Hi

Have you carefully checked the USB circuitry, especially the VREG circuitry, since this is the main cause of issues on custom boards.

In case it proves to be a SW issue, note that there is a industrial quality HS-USB device implementation for the K65/K66 (VCOM and multiple VCOM to UART bridges, Audio, MSD, HID, RNDIS; composite combinations of these as well as USB boot loaders) at
http://www.utasker.com/kinetis/TWR-K65F180M.html
which avoids potential issues in critical developments.

Regards

Mark
Kinetis for professionals: http://http://www.utasker.com/kinetis.html

[edwinkaus]

Hai  Mark Butcher.,

 Thank you for the reply.

I have checked my schematic, in that I am not taking Voltage from VBUS pin,instead we are using another on board power source. up to my knowledge there is no hardware problem .

Also i am attaching USB ckt part , Can you please cross verify once.

Details :

 I am using USB1,

                XTAL1=16MHZ ,

One more thing I have not connected Crystal oscillator for XTAL32 and EXTAL32 pin , Is that make make any problem.  

Any suggestions ..?

Regards  Edwin kaus.

[Hui_Ma]

Hi

Have you modified the <clock_config.h> file with correct crystal clock frequency with below code:

The FRDM-K66F board  is using 12MHz crystal, while your board is using 16MHz crystal:

//#define BOARD_XTAL0_CLK_HZ 12000000U

#define BOARD_XTAL0_CLK_HZ 16000000U

void BOARD_BootClockRUN(void)
{
    const mcg_pll_config_t pll0Config = {
       // .enableMode = 0U, .prdiv = 0x00U, .vdiv = 0x04U,

          .enableMode = 0U, .prdiv = 0x01U, .vdiv = 0x0EU,    //to get PLL output 120MHz clock
    };

Wish it helps.

Have a great day,
Ma Hui
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[edwinkaus]

Hai .,

Yes I have done the above changes what you said , but still its not detecting. 

Anyhow its not matter because USB-PHY using internal clock resource. I am really confused where I did mistake. 

Is there any option to check USB phy with loop back, also how check USB1PFDCLK is proper or not.

[mjbcswitzerland]

Edwin

USB Loopbacks are not possible because it needs an active host to work with.

You mentioned that you would post a diagram earlier but this was not attached so no checking could be made.

If you send/show me a circuit diagram showing the clocks (a UART if available and an LED output  to show the code is operating) I can send you a binary image for your board that will allow you to test HS-USB VCOM.

Regards

Mark

[edwinkaus]

Hai ..,

Thank you for the help, the USB HS device is detecting now, it was having some hardware issue.

Now I want to clarify some other thing related to clock settings.

Now I have connected 16MHZ crystal to XTAL & EXTAL(PIN 72 & 73). But for the Ethernet reuirement I want to replace 16MHZ with 50 MHZ, bcz the same clock I am giving to XTAL pin and also to ethernet PHY. But according to reference manual USB HS PLL works only when XTAL & EXTAL is connected to one of the 12MHZ,16MHZ or 24MHZ.   

Now how can I manage this issue.?

[mjbcswitzerland]

Hi

You need to keep the 16MHz crystal on XTAL & EXTAL and connect a 50MHz PHY clock on ENET_1588_CLKIN (PTE26), configuring its peripheral function.

Regards

Mark
Kinetis for professionals: http://www.utasker.com/kinetis.html

[edwinkaus]

Hai ..,

Thank you very much for the help. 

I have small clarification , if I use one of the clock frequency(50MHZ) other than 12M ,16M,or 24MHZ in XTAL & EXTAL pin , Is there any provision to control output clock of USB1-HS PLL(USB1PFDCLK). Because ENET_1588_CLKIN (PTE26 pin.47) has already used for other functions. I don't have any other choice rather than connecting 50MHZ clock frequency on EXTAL & XTAL pin. 

> What is the required frequency of USB1PFDCLK in USB-HS mode.

>How can I generate USB1PFDCLK clock frequency with 50MHZ clock on EXTAL0 . 

[mjbcswitzerland · Accepted solution]

Edwin

USB1PFDCLK is a signal derived from the 480MHz USB PLL but it is not used by the HS-USB itself; it is simply available for external use in case this could be of advantage (max. 180MHz).

The 480MHz PLL clock is needed by the HS-USB in order for it to be able to operate and it can only be derived from crystal inputs of 12, 16 or 24MHz. If one of these frequencies is not available at the crystal input the PLL cannot be used and therefore HS-USB cannot be used.

Therefore if you can only use a 50MHz clock at the crystal input you cannot use HS-USB. The only way to use both HS-USB and Ethernet is to have the 50MHz clock on ENET_1588_CLKIN

Regards

Mark
Kinetis for professionals: http://www.utasker.com/kinetis.html

[lineage]

Hi Mark,

When you say crystal, do you really mean a crystal connected to XTAL/EXTAL or can it work with an external oscillator connected to EXTAL? I have 24MHz fed to EXTAL but for some reason the USBPHY PLL doesn't show lock.

Thanks

[mjbcswitzerland]

Hi

The clock can be a crystal or an external oscillator - it makes no difference to the PLL.

Check the following too:

- VREGIN0 or VREGIN1 must be valid
- 32kHz slow clock must be enabled too

Regards

Mark

[lineage]

Thanks,

I was clutching at straws. The 24MHz is clocking the rest of the chip OK.

VREGIN - one is from VBUS and the other 3v3. The VREG_OUT looks OK.

32kHz also enabled.

Any other ideas?

Thanks.

[mjbcswitzerland]

Hi

I have a reference here: http://www.utasker.com/kinetis/TWR-K65F180M.html
but it uses a 16MHz crystal.
The initialisation code is below in case you see something.

Regards

Mark

    #if defined ENABLE_HSUSB_TRANSCEIVER
    ENABLE_HSUSB_TRANSCEIVER();
    #endif
    #if defined MPU_AVAILABLE
    MPU_CESR = 0;                                                        // allow concurrent access to MPU controller
    #endif
    FMC_PFAPR |= FMC_FPAPR_USB_HS;                                       // allow USBHS controller to read from Flash

    #if defined KINETIS_WITH_USBPHY                                      // device with integrated HS PHY
        POWER_UP(3, SIM_SCGC3_USBHS);                                    // power up the USB HS controller module
        // Requirements for operation are:
        // - VREGIN0 or VREGIN1 connected to 5V so that 3.3V USB is valid
        // - 32kHz slow clock is enabled
        // - external reference clock is enabled and is 12MHz, 16MHz or 24MHz
        // 
        MCG_C1 |= MCG_C1_IRCLKEN;                                        // 32kHz IRC enable
        OSC0_CR |= OSC_CR_ERCLKEN;                                       // external reference clock enable
        SIM_SOPT2 |= SIM_SOPT2_USBREGEN;                                 // enable USB PHY PLL regulator
        POWER_UP(3, SIM_SCGC3_USBHSPHY);                                 // enable clocks to PHY
        SIM_USBPHYCTL = (SIM_USBPHYCTL_USBVOUTTRG_3_310V | SIM_USBPHYCTL_USBVREGSEL); // 3.310V source VREG_IN1 (in case both are powered)
        USBPHY_TRIM_OVERRIDE_EN = 0x0000001f;                            // override IFR values
        USBPHY_CTRL = (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3); // release PHY from reset and enable its clock
        #if _EXTERNAL_CLOCK == 24000000
        USBPHY_PLL_SIC = (USBPHY_PLL_SIC_PLL_POWER | USBPHY_PLL_SIC_PLL_ENABLE | USBPHY_PLL_SIC_PLL_BYPASS | USBPHY_PLL_SIC_PLL_DIV_SEL_24MHz); // power up PLL to run at 480MHz from 24MHz clock input
        #elif _EXTERNAL_CLOCK == 16000000
        USBPHY_PLL_SIC = (USBPHY_PLL_SIC_PLL_POWER | USBPHY_PLL_SIC_PLL_ENABLE | USBPHY_PLL_SIC_PLL_BYPASS | USBPHY_PLL_SIC_PLL_DIV_SEL_16MHz); // power up PLL to run at 480MHz from 16MHz clock input
        #elif _EXTERNAL_CLOCK == 12000000
        USBPHY_PLL_SIC = (USBPHY_PLL_SIC_PLL_POWER | USBPHY_PLL_SIC_PLL_ENABLE | USBPHY_PLL_SIC_PLL_BYPASS | USBPHY_PLL_SIC_PLL_DIV_SEL_16MHz); // power up PLL to run at 480MHz from 12MHz clock input
        #else
            #error "USB PLL requires an external reference of 12MHz, 16MHz or 24MHz!"
        #endif
        USBPHY_PLL_SIC &= ~(USBPHY_PLL_SIC_PLL_BYPASS);                  // cear the bypass
        USBPHY_PLL_SIC |= (USBPHY_PLL_SIC_PLL_EN_USB_CLKS);              // enable USB clock output from PHY PLL
        while ((USBPHY_PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK) == 0) {        // wait for the PLL to lock
        #if defined _WINDOWS
            USBPHY_PLL_SIC |= USBPHY_PLL_SIC_PLL_LOCK;
        #endif
        }
        USBPHY_PWD = 0;                                                  // for normal operation
        USBPHY_ANACTRL = ((24 << 4) | 4);                                // frac = 24 and  Clk /4
        while ((USBPHY_ANACTRL & 0x80000000) == 0) {
        #if defined _WINDOWS
            USBPHY_ANACTRL |= 0x80000000;
        #endif
        }
        USBPHY_TX |= (1 << 24);                                          // reserved??
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[lineage]

Hi Mark,

More or less what I had. I've tweaked mine to be a functional match just in case it was something subtle, but no change. The only differences are that I don't hit the MPU_CESR and FMC_PFAPR and I assume POWER_UP is just a bit set in the SCGC register. Only other question, whats the

#if defined _WINDOWS
   USBPHY_PLL_SIC | USBPHY_PLL_SIC_PLL_LOCK;
#endif


I presume you don't need to do that normally? ie the PLL lock status does work?

Thanks for your help, at least that tells me I've not missed anything in the basic setup.

[mjbcswitzerland]

Hi

The parts with _WINDOWS are used by the uTasker simulator when running the code and are not used by cross-compiled code.

Regards

Mark

[lineage]

Hi Mark,

Think we have found the problem. So I'll post it here in case other people hit the same issue.

There is an Errata..

e9712: USB-PHY: USB PHY PLL does not lock when MCGC2[EREFS] = 0 (external oscillator clock)

It looks like to get the USB PLL to lock, the OSC block must be configured as if you had a crystal even if you are using an external oscillator.. So even though I'm using an external oscillator on EXTAL having set EREFS=1 I'm now seeing lock. However that also seems to have some unfortunate consequences and has changed the mode on the XTAL pin which was being used for something else. Don't now whether I can fix that yet, the errata workarounf info is rather brief.

Cheers

[mjbcswitzerland]

Hi

Thanks for the feedback - my version of the K65/K65 errata (used for the uTasker HS USB development) didn't include this - I see it was added in a more recent revision.

I have thus added the workaround as I have understood it to the code as below. I am assuming that the "pretend" flag is only needed during the lock phase and afterwards can be removed again.

In case there are problems with the workaround (I won't test it at the moment due to other work) which make it unrealistic I would change the conditional code to #error "Crystal clock should be used for HS USB!!!" so that it won't build if tried.

Note that I use an errata header file that automatically selects the errata IDs for each chip mask so when the K65, K66 or K26 (MASK_0N65N) are used the appropriate workarounds are enabled in code as required.

Regards

Mark

        #if defined ERRATA_ID_9712 && defined EXTERNAL_CLOCK
        // Error 9712 workaround is being enabled - advise use of crystal rather than external clock!
        //
        MCG_C2 |= MCG_C2_EREFS; // pretend that crystal is being used so that the PLL will lock
        #endif
        USBPHY_PLL_SIC &= ~(USBPHY_PLL_SIC_PLL_BYPASS);                  // cear the bypass
        USBPHY_PLL_SIC |= (USBPHY_PLL_SIC_PLL_EN_USB_CLKS);  // enable USB clock output from PHY PLL
        while ((USBPHY_PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK) == 0) {  // wait for the PLL to lock
        #if defined _WINDOWS
            USBPHY_PLL_SIC |= USBPHY_PLL_SIC_PLL_LOCK;
        #endif
        }
        #if defined ERRATA_ID_9712 && defined EXTERNAL_CLOCK
        // Error 9712 workaround is being enabled - advise use of crystal rather than external clock!
        //
        MCG_C2 &= ~MCG_C2_EREFS;   // remove the external reference from oscillator requested flag
        #endif

[lineage]

Hi,

I think thats an assumption too far.. Don't negate EREFS after lock. I think its a clock routing problem not a pll lock problem.

Cheers

[edwinkaus]

Hello.,

I have some problem in USB driver. The device is not properly detecting, In PC its showing unknown device, also I tried to update driver but its not happening. I have checked the properties of unknown device it doesn't have any information like PID,VID etc.

I have debug the code , I am getting reset interrupt, but not getting SOF(start of frame interrupt),what's the mistake, Is there any changes has to be done in SDK_2.0_MK66FN2M0xxx18 stack.

please get back to me as soon as possible. 

thank you..,