Hi Martyn, Thanks for the reply.
Yes I do mean UART0_C5->RDMAE & UART1_C4->RDMAS. Mistakenly swapped the register names in the original post.
The DMA_Init routine for UART0 to UART1 (not working data direction) is as below
void UART0to1_DMA_Init(){
// Setting up the NVIC for DMA0 interrupt
NVIC_ICPR |= (0x01); // Clear any pending interrupt for DMA0
NVIC_ISER |= (0x01); // Enable the interrupt for DMA0 module
NVIC_IPR0 |= (0x02<<6); // Set the priority to be 2
/* Enable the clock to DMA MUX and DMA */
SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
// Disable the DMA0 channel
DMAMUX0_CHCFG0 = 0x00;
// Clear pending errors or the done bit for channel 1
if (((DMA_DSR_BCR0 & DMA_DSR_BCR_DONE_MASK) == DMA_DSR_BCR_DONE_MASK)
| ((DMA_DSR_BCR0 & DMA_DSR_BCR_BES_MASK) == DMA_DSR_BCR_BES_MASK)
| ((DMA_DSR_BCR0 & DMA_DSR_BCR_BED_MASK) == DMA_DSR_BCR_BED_MASK)
| ((DMA_DSR_BCR0 & DMA_DSR_BCR_CE_MASK) == DMA_DSR_BCR_CE_MASK))
DMA_DSR_BCR0 |= DMA_DSR_BCR_DONE_MASK;
// Set Source Address for DMA0
DMA_SAR0 = 0x4006A007;
// Set DMA byte counter
DMA_DSR_BCR0 = DMA_DSR_BCR_BCR(0xFFFFF);
// Clear the bits config bits
DMA_DCR0 &= ~(DMA_DCR_SSIZE_MASK| DMA_DCR_DSIZE_MASK);
// Set the transfer attributes
DMA_DCR0 |= (DMA_DCR_EINT_MASK
| DMA_DCR_SSIZE(1)
| DMA_DCR_DSIZE(1)
| DMA_DCR_CS_MASK
| DMA_DCR_ERQ_MASK
);
// Set Destination Address
DMA_DAR0 = 0x4006B007;
// Enables the DMA channel and select the DMA Channel Source
DMAMUX0_CHCFG0 = 0x02; // Source set to uart0 receive
DMAMUX0_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK;
}
The DMA interrupt handler is as below
void DMA0_IRQHandler()
{
// Clear pending errors or the done bit
if (((DMA_DSR_BCR0 & DMA_DSR_BCR_DONE_MASK) == DMA_DSR_BCR_DONE_MASK)
| ((DMA_DSR_BCR0 & DMA_DSR_BCR_BES_MASK) == DMA_DSR_BCR_BES_MASK)
| ((DMA_DSR_BCR0 & DMA_DSR_BCR_BED_MASK) == DMA_DSR_BCR_BED_MASK)
| ((DMA_DSR_BCR0 & DMA_DSR_BCR_CE_MASK) == DMA_DSR_BCR_CE_MASK))
{
DMA_DSR_BCR0 |= DMA_DSR_BCR_DONE_MASK;
// Reload the BCR
DMA_DSR_BCR0 = DMA_DSR_BCR_BCR(0xFFFFF);
}
}
And finally the UART0 init (skipping the baud rate generation code)
/* Selecting the clock source for the UART0. We are selecting the MCGFLLCLK, 24Mhz */
SIM_SOPT2 |= (0x1<<16); // Set PLLFLLSEL
SIM_SOPT2 |= SIM_SOPT2_UART0SRC(0x01); // Set UART Source
/* Enable the clock to UART0 */
SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;
/* Enable the pins of UART output */
PORTA_PCR1 |= PORT_PCR_MUX(2); // Select the function of PTA1 to be UART0RX
PORTA_PCR2 |= PORT_PCR_MUX(2); // Select the function of PTA2 to be UART0TX
UART0_C2 &= ~(UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK); // Turn off the receiver and transmitter
/* set the baud rate registers
.
.
.
*/
UART0_C2 |= (UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK); /* Enable the transmitter and receiver */
UART0_C5 |= UARTLP_C5_RDMAE_MASK; // Turn on DMA request for UART0
and for UART1
/* Enable the clock to UART1 */
SIM_SCGC4 |= SIM_SCGC4_UART1_MASK;
/* Enable the pins of UART output */
PORTE_PCR0 |= PORT_PCR_MUX(3); // Select the function of PTE0 to be UART1TX
PORTE_PCR1 |= PORT_PCR_MUX(3); // Select the function of PTE1 to be UART1RX
/* Make sure that the Transmitter and Receiver is disabled */
UART1_C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
UART1_C1 = 0x0; // Set default settings
// Enable the interrupt and DMA request
UART1_C4 |= UART_C4_RDMAS_MASK; // Turning on receive DMA req
// Enable the receive interrupt
UART1_C2 |= UART_C2_RIE_MASK;
/* Enable receiver and transmitter */
UART1_C2 |= (UART_C2_TE_MASK | UART_C2_RE_MASK );
as for the requirement to turn on UART1 Receive interrupt, it is mentioned inside the RM for RDMAS:
NOTE: If RIE is cleared, the RDRF DMA and RDRF interrupt request signals are not asserted when the
RDRF flag is set, regardless of the state of RDMAS.
0 If RIE is set and the RDRF flag is set, the RDRF interrupt request signal is asserted to request
interrupt service.
1 If RIE is set and the RDRF flag is set, the RDRF DMA request signal is asserted to request a DMA
transfer.
So to pass data from UART1 to UART0 using DMA triggered at UART1 receive (which is working) requires RIE to be set.
