Hello Lu,
In MCG_C4 register, you can look at default FLL Factor for your MCU (DRST_DRS and DMX32 fields), by default, the FLL factor is 640 so DCO Range is between 20-25 MHz, also notice that there is not lower frequency than 20 MHz for DCO.
Other thing that you can do is to check Slow Internal Reference Clock Fine Trim settings (SCFTRIM field on MCG_C4 register) in both boards, maybe the trimming value is not the same in both board and that is why MCGOUTCLK frequency is different in both boards.
Hope this helps,
Regards,
Isaac
Hello Lu Wang,
After Reset, FEI mode is configured by default, in this mode, MCGOUTCLK clock is taken from FLL that is internally using the Slow Internal Reference clock (32 kHz) and multiplication factor of 640, so, MCGOUTCLK clock is 20.97 MHz.
Basically, to corroborate that MCU is configured in FEI mode, you need to validate that:
- MCG_S[CLKST] field is 0x00 (It means that FLL is selected)
- MCG_S[IREFST] field is 1 (It means that FLL reference clock is the internal reference clock)
- MCG_S[PLLST] filed is 0 (it means that FLL output is used instead of PLL)
If these conditions are accomplished, then, you are working on FEI mode.
About UART clocking, in section 12.7.7 UART clocking from Reference Manual, it says that UART0 and UART1 operate from core/system clock and all other UART modules opera from Bus clock.
Remember that core/system clock is taken from MCGOUTCLK / OUTDIV1 value, that is set in SIM_CLKDIV1 register:
So, if OUTDIV1 is set to 0, then Core\System clock is equal to MCGOUTCLK / 1 = MCGOUTCLK. (20.97MHz at reset).
About the issue you are facing, just validate that FLL is using default values so Core clock is set to 20.97MHz and under this value, calculate SBR and BRFD values.
I hope this can help you!
Best Regards,
Isaac Avila
