I want to establish Ethernet connection in my project. Two boards connected with a tower rack.
First I configure related pins
void BOARD_InitPins(void)
{
/* PORTA18 (pin 72) is configured as EXTAL0 */
PORT_SetPinMux(PORTA, 18U, kPORT_PinDisabledOrAnalog);
/* PORTE11 (pin 14) is configured as PTE11 - LEDR */
PORT_SetPinMux(PORTE, 11U, kPORT_MuxAsGpio);
/* PORTE12 (pin 15) is configured as PTE12 - LEDG */
PORT_SetPinMux(PORTE, 12U, kPORT_MuxAsGpio);
/* PORTE29 (pin 37) is configured as PTE29 - LEDB */
PORT_SetPinMux(PORTE, 29U, kPORT_MuxAsGpio);
/* PORTE30 (pin 38) is configured as PTE30 - LEDO */
PORT_SetPinMux(PORTE, 30U, kPORT_MuxAsGpio);
/* PORTA10 (pin 62) is configured as MII0_RXD2 */
PORT_SetPinMux(PORTA, 10U, kPORT_MuxAlt5);
/* PORTA11 (pin 63) is configured as MII0_RXCLK */
PORT_SetPinMux(PORTA, 11U, kPORT_MuxAlt5);
/* PORTA12 (pin 64) is configured as MII0_RXD1 */
PORT_SetPinMux(PORTA, 12U, kPORT_MuxAlt5);
/* PORTA13 (pin 65) is configured as MII0_RXD0 */
PORT_SetPinMux(PORTA, 13U, kPORT_MuxAlt5);
/* PORTA14 (pin 66) is configured as MII0_RXDV */
PORT_SetPinMux(PORTA, 14U, kPORT_MuxAlt5);
/* PORTA15 (pin 67) is configured as MII0_TXEN */
PORT_SetPinMux(PORTA, 15U, kPORT_MuxAlt5);
/* PORTA16 (pin 68) is configured as MII0_TXD0 */
PORT_SetPinMux(PORTA, 16U, kPORT_MuxAlt5);
/* PORTA17 (pin 69) is configured as MII0_TXD1 */
PORT_SetPinMux(PORTA, 17U, kPORT_MuxAlt5);
/* PORTA25 (pin 76) is configured as MII0_TXCLK */
PORT_SetPinMux(PORTA, 25U, kPORT_MuxAlt5);
/* PORTA26 (pin 77) is configured as MII0_TXD3 */
PORT_SetPinMux(PORTA, 26U, kPORT_MuxAlt5);
/* PORTA27 (pin 78) is configured as MII0_CRS */
PORT_SetPinMux(PORTA, 27U, kPORT_MuxAlt5);
/* PORTA28 (pin 79) is configured as MII0_TXER */
PORT_SetPinMux(PORTA, 28U, kPORT_MuxAlt5);
/* PORTA29 (pin 80) is configured as MII0_COL */
PORT_SetPinMux(PORTA, 29U, kPORT_MuxAlt5);
/* PORTA5 (pin 55) is configured as MII0_RXER */
PORT_SetPinMux(PORTA, 5U, kPORT_MuxAlt4);
const port_pin_config_t porta7_pin59_config = {/* Internal pull-up/down resistor is disabled */
kPORT_PullDisable,
/* Slow slew rate is configured */
kPORT_SlowSlewRate,
/* Passive filter is disabled */
kPORT_PassiveFilterDisable,
/* Open drain is enabled */
kPORT_OpenDrainEnable,
/* Low drive strength is configured */
kPORT_LowDriveStrength,
/* Pin is configured as MII0_MDIO */
kPORT_MuxAlt5,
/* Pin Control Register fields [15:0] are not locked */
kPORT_UnlockRegister};
/* PORTA7 (pin 59) is configured as MII0_MDIO */
PORT_SetPinConfig(PORTA, 7U, &porta7_pin59_config);
/* PORTA8 (pin 60) is configured as MII0_MDC */
PORT_SetPinMux(PORTA, 8U, kPORT_MuxAlt5);
/* PORTA9 (pin 61) is configured as MII0_RXD3 */
PORT_SetPinMux(PORTA, 9U, kPORT_MuxAlt5);
/* PORTC16 (pin 123) is configured as ENET0_1588_TMR0 */
PORT_SetPinMux(PORTC, 16U, kPORT_MuxAlt4);
/* PORTC17 (pin 124) is configured as ENET0_1588_TMR1 */
PORT_SetPinMux(PORTC, 17U, kPORT_MuxAlt4);
/* PORTC18 (pin 125) is configured as ENET0_1588_TMR2 */
PORT_SetPinMux(PORTC, 18U, kPORT_MuxAlt4);
/* PORTC19 (pin 126) is configured as ENET0_1588_TMR3 */
PORT_SetPinMux(PORTC, 19U, kPORT_MuxAlt4);
}
Then I try to configure the Phy on board (KSZ8041NL).
sysClock = CLOCK_GetFreq(kCLOCK_CoreSysClk);
status = PHY_Init(ENET, 0, sysClock);
if(status != kStatus_Success)
{
printf("PHY Error\n");
}
And I get an error. What do I miss?
I checked the PHY's clock it's OK 50 Mhz.
Inside PHY_Init I see
CLOCK_EnableClock(s_enetClock[instance]);
ENET_SetSMI(base, srcClock_Hz, false);
So I suppose ENET peripherial is configured for PHY communication.
But on PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg) I fail.
May be the arguments phyAddr (0) , PHY_ID1_REG (2) are wrong? What should it be?